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* FSL IPUv3 Display/FB
The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics
subsystem in an application processor. The goal of the IPU is to provide
comprehensive support for the flow of data from an image sensor or/and to a
display device.
Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC.
Each IPU unit has two display interfaces.
For LDB/LVDS panel, there are two LVDS channels(LVDS0 and LVDS1) which can
transfer video data, these two channels can be used as
split/dual/single/separate mode.
-split mode means display data from DI0 or DI1 will send to both channels
LVDS0+LVDS1.
-dual mode means display data from DI0 or DI1 will be duplicated on LVDS0
and LVDS1, it said, LVDS0 and LVDS1 has the same content.
-single mode means only work for DI0/DI1->LVDS0 or DI0/DI1->LVDS1.
-separate mode means you can make DI0/DI1->LVDS0 and DI0/DI1->LVDS1 work
at the same time.
"ldb=spl0/1" -- split mode on DI0/1
"ldb=dul0/1" -- dual mode on DI0/1
"ldb=sin0/1" -- single mode on LVDS0/1
"ldb=sep0/1" -- separate mode begin from LVDS0/1
Required properties for IPU:
- bypass_reset :Bypass reset to avoid display channel being.
stopped by probe since it may start to work in bootloader: 0 or 1.
- compatible : should be "fsl,imx6q-ipu".
- reg : the register address range.
- interrupts : the error and sync interrupts request.
- clocks : the clock sources that it depends on.
- clock-names: the related clock names.
- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in
Documentation/devicetree/bindings/reset/ for details.
Required properties for fb:
- compatible : should be "fsl,mxc_sdc_fb".
- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi".
- mode_str : video mode string: "LDB-XGA" or "LDB-1080P60" for ldb,
"CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel,
"1920x1080M@60" for hdmi.
- default_bpp : default bits per pixel: 8/16/24/32
- int_clk : use internal clock as pixel clock: 0 or 1
- late_init : to avoid display channel being re-initialized
as we've probably setup the channel in bootloader: 0 or 1
- interface_pix_fmt : display interface pixel format as below:
RGB666 IPU_PIX_FMT_RGB666
RGB565 IPU_PIX_FMT_RGB565
RGB24 IPU_PIX_FMT_RGB24
BGR24 IPU_PIX_FMT_BGR24
GBR24 IPU_PIX_FMT_GBR24
YUV444 IPU_PIX_FMT_YUV444
LVDS666 IPU_PIX_FMT_LVDS666
YUYV IPU_PIX_FMT_YUYV
UYVY IPU_PIX_FMT_UYVY
YVYV IPU_PIX_FMT_YVYU
VYUY IPU_PIX_FMT_VYUY
Required properties for display:
- compatible : should be "fsl,lcd" for lcd panel, "fsl,imx6q-ldb" for ldb
- ipu_id : ipu id for the first display device: 0 or 1
- disp_id : display interface id for the first display interface: 0 or 1
- default_ifmt : save as above display interface pixel format for lcd
- pinctrl-names : should be "default"
- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
IPU connected.
- sec_ipu_id : secondary ipu id for the second display device(ldb only): 0 or 1
- sec_disp_id : secondary display interface id for the second display
device(ldb only): 0 or 1
- ext_ref : reference resistor select for ldb only: 0 or 1
- mode : ldb mode as below:
spl0 LDB_SPL_DI0
spl1 LDB_SPL_DI1
dul0 LDB_DUL_DI0
dul1 LDB_DUL_DI1
sin0 LDB_SIN0
sin1 LDB_SIN1
sep0 LDB_SEP0
sep1 LDB_SEP1
Example for IPU:
ipu1: ipu@02400000 {
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x400000>;
interrupts = <0 6 0x4 0 5 0x4>;
clocks = <&clks 130>, <&clks 131>, <&clks 132>,
<&clks 39>, <&clks 40>,
<&clks 135>, <&clks 136>;
clock-names = "bus", "di0", "di1",
"di0_sel", "di1_sel",
"ldb_di0", "ldb_di1";
resets = <&src 2>;
bypass_reset = <0>;
};
Example for fb:
fb0 {
compatible = "fsl,mxc_sdc_fb";
disp_dev = "ldb";
interface_pix_fmt = "RGB666";
mode_str ="LDB-XGA";
default_bpp = <16>;
int_clk = <0>;
late_init = <0>;
status = "okay";
};
Example for ldb display:
ldb@020e0000 {
ipu_id = <1>;
disp_id = <0>;
ext_ref = <1>;
mode = "sep0";
sec_ipu_id = <1>;
sec_disp_id = <1>;
status = "okay";
};
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