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Hisilicon hix5hd2 gmac controller
Required properties:
- compatible: should contain one of the following SoC strings:
* "hisilicon,hix5hd2-gemac"
* "hisilicon,hi3798cv200-gemac"
and one of the following version string:
* "hisilicon,hisi-gemac-v1"
* "hisilicon,hisi-gemac-v2"
- reg: specifies base physical address(s) and size of the device registers.
The first region is the MAC register base and size.
The second region is external interface control register.
- interrupts: should contain the MAC interrupt.
- #address-cells: must be <1>.
- #size-cells: must be <0>.
- phy-mode: see ethernet.txt [1].
- phy-handle: see ethernet.txt [1].
- mac-address: see ethernet.txt [1].
- clocks: clock phandle and specifier pair.
- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).
- resets: should contain the phandle to the MAC core reset signal(optional),
the MAC interface reset signal(optional)
and the PHY reset signal(optional).
- reset-names: contain the reset signal name "mac_core"(optional),
"mac_ifc"(optional) and "phy"(optional).
- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
The 1st cell is reset pre-delay in micro seconds.
The 2nd cell is reset pulse in micro seconds.
The 3rd cell is reset post-delay in micro seconds.
- PHY subnode: inherits from phy binding [2]
[1] Documentation/devicetree/bindings/net/ethernet.txt
[2] Documentation/devicetree/bindings/net/phy.txt
Example:
gmac0: ethernet@f9840000 {
compatible = "hisilicon,hi3798cv200-gemac", "hisilicon,hisi-gemac-v2";
reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
interrupts = <0 71 4>;
#address-cells = <1>;
#size-cells = <0>;
phy-mode = "rgmii";
phy-handle = <&phy2>;
mac-address = [00 00 00 00 00 00];
clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
clock-names = "mac_core", "mac_ifc";
resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
reset-names = "mac_core", "mac_ifc", "phy";
hisilicon,phy-reset-delays-us = <10000 10000 30000>;
phy2: ethernet-phy@2 {
reg = <2>;
};
};
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