blob: 431add192342ec320b4e0718b22f45aa4f7630c5 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
Cavium, Inc. OCTEON SOC SPI master controller.
Required properties:
- compatible : "cavium,octeon-3010-spi"
- reg : The register base for the controller.
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
Child nodes as per the generic SPI binding.
Example:
spi@1070000001000 {
compatible = "cavium,octeon-3010-spi";
reg = <0x10700 0x00001000 0x0 0x100>;
interrupts = <0 58>;
#address-cells = <1>;
#size-cells = <0>;
eeprom@0 {
compatible = "st,m95256", "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
spi-cpha;
spi-cpol;
pagesize = <64>;
size = <32768>;
address-width = <16>;
};
};
|
