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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1075000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
soc {
gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x0 0x0>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr";
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
<0 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_DUMMY>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
power-domains = <&gpc 1>;
};
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@02000000 {
vpu@02040000 {
iramsize = <0>;
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
dcic2: dcic@020e8000 {
clocks = <&clks IMX6QDL_CLK_DCIC1 >,
<&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
clock-names = "dcic", "disp-axi";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@02100000 {
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6DL_CLK_I2C4>;
status = "disabled";
};
};
};
};
&i2c3 {
max17135@48 {
compatible = "maxim,max17135";
reg = <0x48>;
vneg_pwrup = <1>;
gvee_pwrup = <1>;
vpos_pwrup = <2>;
gvdd_pwrup = <1>;
gvdd_pwrdn = <1>;
vpos_pwrdn = <2>;
gvee_pwrdn = <1>;
vneg_pwrdn = <1>;
SENSOR-supply = <®_sensor>;
gpio_pmic_pwrgood = <&gpio2 21 0>;
gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
gpio_pmic_wakeup = <&gpio3 20 0>;
gpio_pmic_v3p3 = <&gpio2 20 0>;
gpio_pmic_intr = <&gpio2 25 0>;
regulators {
DISPLAY_reg: DISPLAY {
regulator-name = "DISPLAY";
};
GVDD_reg: GVDD {
/* 20v */
regulator-name = "GVDD";
};
GVEE_reg: GVEE {
/* -22v */
regulator-name = "GVEE";
};
HVINN_reg: HVINN {
/* -22v */
regulator-name = "HVINN";
};
HVINP_reg: HVINP {
/* 20v */
regulator-name = "HVINP";
};
VCOM_reg: VCOM {
regulator-name = "VCOM";
/* 2's-compliment, -4325000 */
regulator-min-microvolt = <0xffbe0178>;
/* 2's-compliment, -500000 */
regulator-max-microvolt = <0xfff85ee0>;
};
VNEG_reg: VNEG {
/* -15v */
regulator-name = "VNEG";
};
VPOS_reg: VPOS {
/* 15v */
regulator-name = "VPOS";
};
V3P3_reg: V3P3 {
regulator-name = "V3P3";
};
};
};
};
&iomuxc {
epdc {
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
>;
};
};
};
&epdc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_epdc_0>;
V3P3-supply = <&V3P3_reg>;
VCOM-supply = <&VCOM_reg>;
DISPLAY-supply = <&DISPLAY_reg>;
status = "okay";
};
&ldb {
compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
"di2_sel",
"ldb_di0_div_3_5", "ldb_di1_div_3_5",
"ldb_di0_div_7", "ldb_di1_div_7",
"ldb_di0_div_sel", "ldb_di1_div_sel";
};
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