path: root/arch/arm/boot/dts/imx6qdl-apalis.dtsi

/*
 * Copyright 2014 Toradex AG
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <dt-bindings/input/input.h>

/ {
	model = "Toradex Apalis iMX6Q  Module";
	compatible = "toradex,apalis_imx6q", "fsl,imx6q";

	aliases {
		mxcfb0 = &mxcfb1;
		mxcfb1 = &mxcfb2;
		mxcfb2 = &mxcfb3;
		mxcfb3 = &mxcfb4;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm4 0 5000000>;
		status = "disabled";
	};

	clocks {
		clk24m: clk24m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

/*
 * DDC_I2C: I2C2_SDA/SCL on MXM3 pin 205/207
 */
	i2cddc: i2c@0 {
		compatible = "i2c-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c_ddc>;
		gpios = <&gpio3 16 0 /* sda */
			 &gpio2 30 0 /* scl */
			>;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "okay";
	};

	lcd: lcd@0 {
		compatible = "fsl,lcd";
		ipu_id = <0>;
		disp_id = <1>;
		default_ifmt = "RGB24";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu1_t1>;
		status = "disabled";
	};

	memory {
		/* This node is rewritten by U-Boot with the actual memory size */
		reg = <0x10000000 0x80000000>;
	};

#if 0
	mxcfb1: fb@0 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "mipi_dsi";
		interface_pix_fmt = "RGB666";
		mode_str ="LDB-XGA";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
#else
	mxcfb1: fb@0 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "ldb";
		interface_pix_fmt = "LVDS666";
		mode_str ="LDB-XGA";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
#endif
	};

	mxcfb2: fb@1 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "hdmi";
		interface_pix_fmt = "RGB24";
		mode_str ="1920x1080M@60";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
	};

	mxcfb3: fb@2 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "lcd";
		interface_pix_fmt = "RGB565";
		mode_str ="CLAA-WVGA";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
	};

#if 0
	mxcfb4: fb@3 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "ldb";
		interface_pix_fmt = "RGB666";
		mode_str ="LDB-XGA";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
	};
#else
	mxcfb4: fb@3 {
		compatible = "fsl,mxc_sdc_fb";
		disp_dev = "vdac";
		interface_pix_fmt = "RGB565";
		mode_str ="LDB-XGA";
		default_bpp = <16>;
		int_clk = <0>;
		late_init = <0>;
		status = "disabled";
	};
#endif

	regulators {
		compatible = "simple-bus";

		reg_1p8v: 1p8v {
			compatible = "regulator-fixed";
			regulator-name = "1P8V";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		reg_2p5v: 2p5v {
			compatible = "regulator-fixed";
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: 3p3v {
			compatible = "regulator-fixed";
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		reg_usb_otg_vbus: usb_otg_vbus {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
			regulator-name = "usb_otg_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 22 0>;
			enable-active-high;
			status = "disabled";
		};

		/* on module usb hub */
		reg_usb_host_vbus_hub: usb_host_vbus_hub {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
			regulator-name = "usb_host_vbus_hub";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio3 28 0>;
			startup-delay-us = <2000>;
			enable-active-high;
			status = "okay";
		};
		
		reg_usb_host_vbus: usb_host_vbus {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
			regulator-name = "usb_host_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio =  <&gpio1 0 0>;
			enable-active-high;
			vin-supply = <&reg_usb_host_vbus_hub>;
			status = "disabled";
		};
	};

	sound {
		compatible = "fsl,imx6q-apalis-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6q-apalis-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};

	sound_hdmi: sound-hdmi {
		compatible = "fsl,imx6q-audio-hdmi",
			     "fsl,imx-audio-hdmi";
		model = "imx-audio-hdmi";
		hdmi-controller = <&hdmi_audio>;
		status = "disabled";
	};

	sound_spdif: sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
		spdif-in;
		status = "disabled";
	};

	vdac: vdac@0 {
		compatible = "fsl,vdac";
		ipu_id = <1>;
		disp_id = <0>;
		default_ifmt = "RGB565";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu2_t1>;
		status = "disabled";
	};

	v4l2_out {
		compatible = "fsl,mxc_v4l2_output";
		status = "okay";
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux_t1 &pinctrl_audmux_mclk_1>;
	status = "okay";
};

/* Apalis SPI1 */
&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio5 25 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_t1 &pinctrl_spi_cs1>;
	status = "disabled";
};

/* Apalis SPI2 */
&ecspi2 {
	fsl,spi-num-chipselects = <1>;
	cs-gpios = <&gpio2 26 0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2_t1 &pinctrl_spi_cs2>;
	status = "disabled";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet_4 &pinctrl_enet_ctrl_1>;
	phy-mode = "rgmii";
	/*phy-reset-gpios = <&gpio1 25 0>;*/
	status = "okay";

	#address-cells = <0>;
	#size-cells = <1>;
	phy_int {
		reg = <0x6>;
		interrupt-parent = <&gpio1>;
		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1_t1>;
	status = "disabled";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2_1>;
	status = "disabled";
};

&hdmi_audio {
	status = "okay";
};

&hdmi_cec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_cec_2>;
	status = "disabled";
};

&hdmi_core {
	ipu_id = <0>;
	disp_id = <0>;
	status = "disabled";
};

&hdmi_video {
	fsl,phy_reg_vlev = <0x0294>;
	fsl,phy_reg_cksymtx = <0x800d>;
	status = "disabled";
};

/*
 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
 * board)
 */
&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1_2>;
	status = "disabled";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2_2>;
	status = "okay";

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};

	/* STMPE811 touch screen controller */
	stmpe811@41 {
		compatible = "st,stmpe811";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_touch_int_1>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x41>;
		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
		interrupt-parent = <&gpio4>;
		interrupt-controller;
		id = <0>;
		blocks = <0x5>;
		irq-trigger = <0x1>;
		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			reg = <0>;
			/* 3.25 MHz ADC clock speed */
			st,adc-freq = <1>;
			/* 8 sample average control */
			st,ave-ctrl = <3>;
			/* 7 length fractional part in z */
			st,fraction-z = <7>;
			/*
			 * 50 mA typical 80 mA max touchscreen drivers
			 * current limit value
			 */
			st,i-drive = <1>;
			/* 12-bit ADC */
			st,mod-12b = <1>;
			/* internal ADC reference */
			st,ref-sel = <0>;
			/* ADC converstion time: 80 clocks */
			st,sample-time = <4>;
			/* 1 ms panel driver settling time */
			st,settling = <3>;
			/* 5 ms touch detect interrupt delay */
			st,touch-det-delay = <5>;
		};
		stmpe_adc {
			compatible = "st,stmpe-adc";
			/* 3.25 MHz ADC clock speed */
			st,adc-freq = <1>;
			/* 12-bit ADC */
			st,mod-12b = <1>;
			/* internal ADC reference */
			st,ref-sel = <0>;
			/* ADC converstion time: 80 clocks */
			st,sample-time = <4>;
		};
	};
};

/*
 * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 pin 201/203 (unused)
 */
&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "recovery";
	pinctrl-0 = <&pinctrl_i2c3_1>;
	pinctrl-1 = <&pinctrl_i2c3_recovery_1>;
	gpios = <&gpio3 18 0 /* sda */
	         &gpio3 17 0 /* scl */
	        >;
	status = "disabled";
};

/* PAD Ctrl Values for Common Settings */
#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/
#define PAD_CTRL_NO 0x80000000

&iomuxc {
	audmux {

		pinctrl_audmux_t1: audmux-t1 {
			fsl,pins = <
				MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
				MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x130b0
				MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
				MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
			>;
		};
	};

	ecspi1 {

		pinctrl_ecspi1_t1: ecspi1grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
				MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
				MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
			>;
		};
	};

	ecspi2 {
		pinctrl_ecspi2_t1: ecspi2grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
				MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
				MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
			>;
		};
	};

	flexcan1 {

		pinctrl_flexcan1_t1: flexcan1grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
				MX6QDL_PAD_GPIO_8__FLEXCAN1_RX   0x80000000
			>;
		};
	};

	imx6q-apalis {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reset_moci &pinctrl_emmc_reset_1>;
		pinctrl_apalis_gpio1: apalis_gpio1-1 {
			fsl,pins = <
				/* Apalis GPIO */
				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		PAD_CTRL_HYS_PD	/* Apalis GPIO1 */
			>;
		};
		pinctrl_apalis_gpio2: apalis_gpio2-1 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D5__GPIO2_IO05		PAD_CTRL_HYS_PD	/* Apalis GPIO2 */
			>;
		};
		pinctrl_apalis_gpio3: apalis_gpio3-1 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D6__GPIO2_IO06		PAD_CTRL_HYS_PD	/* Apalis GPIO3 */
			>;
		};
		pinctrl_apalis_gpio4: apalis_gpio4-1 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_D7__GPIO2_IO07		PAD_CTRL_HYS_PD	/* Apalis GPIO4 */
			>;
		};
		pinctrl_apalis_gpio5: apalis_gpio5-1 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_RB0__GPIO6_IO10	PAD_CTRL_HYS_PD	/* Apalis GPIO5 */
			>;
		};
		pinctrl_apalis_gpio6: apalis_gpio6-1 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09	PAD_CTRL_HYS_PD	/* Apalis GPIO6 */
			>;
		};
		pinctrl_apalis_gpio7: apalis_gpio7-1 {
			fsl,pins = <
				MX6QDL_PAD_GPIO_2__GPIO1_IO02		PAD_CTRL_HYS_PD	/* Apalis GPIO7 */
			>;
		};
		pinctrl_apalis_gpio8: apalis_gpio8-1 {
			fsl,pins = <
				MX6QDL_PAD_GPIO_6__GPIO1_IO06		PAD_CTRL_HYS_PD	/* Apalis GPIO8 */
			>;
		};
		pinctrl_audmux_mclk_1: audmux_mclk-1 {
			fsl,pins = <
				MX6QDL_PAD_GPIO_5__CCM_CLKO1		0x000b0		/* SGTL5000 sys_mclk */
			>;
		};
		pinctrl_emmc_reset_1: emmc_reset-1 {
			fsl,pins = <
				MX6QDL_PAD_SD3_RST__GPIO7_IO08		PAD_CTRL_PU_22k	/* eMMC reset, leave it alone */
			>;
		};
		pinctrl_cam_mclk_t2: cam_mclk-t2 {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CS2__CCM_CLKO2		0x000b0		/* CAM sys_mclk */
			>;
		};
		pinctrl_enet_ctrl_1: enet_ctrl-1 {
			fsl,pins = <
				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	PAD_CTRL_NO	/* ENET phy reset */
				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	PAD_CTRL_HYS_PU	/* ENET phy interrupt */
			>;
		};
		pinctrl_gpio_keys: gpio_keys {
			fsl,pins = <
				MX6QDL_PAD_GPIO_4__GPIO1_IO04		PAD_CTRL_HYS_PU	/* Power Button */
				>;
		};
		pinctrl_i2c_ddc: i2c_ddc {
			fsl,pins = <
				MX6QDL_PAD_EIM_EB2__GPIO2_IO30		PAD_CTRL_HYS_PU	/* DDC bitbang */
				MX6QDL_PAD_EIM_D16__GPIO3_IO16		PAD_CTRL_HYS_PU	/* DDC bitbang */
				>;
		};
		pinctrl_i2c3_recovery_1: i2c2_recovery {
			fsl,pins = <
				MX6QDL_PAD_EIM_D17__GPIO3_IO17		PAD_CTRL_HYS_PU	/* DDC bitbang */
				MX6QDL_PAD_EIM_D18__GPIO3_IO18		PAD_CTRL_HYS_PU	/* DDC bitbang */
			>;
		};
		pinctrl_mmc_cd: gpio_mmc_cd {
			fsl,pins = <
				MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		PAD_CTRL_NO	/* MMC1 CD */
				>;
		};
		pinctrl_regulator_usbh_pwr: gpio_regulator_usbh_pwr {
			fsl,pins = <
				MX6QDL_PAD_GPIO_0__GPIO1_IO00		PAD_CTRL_PU_22k	/* USBH_EN */
				>;
		};
		pinctrl_regulator_usbhub_pwr: gpio_regulator_usbhub_pwr {
			fsl,pins = <
				MX6QDL_PAD_EIM_D28__GPIO3_IO28		PAD_CTRL_PU_22k	/* USBH_HUB_EN */
				>;
		};
		pinctrl_regulator_usbotg_pwr: gpio_regulator_usbotg_pwr {
			fsl,pins = <
				MX6QDL_PAD_EIM_D22__GPIO3_IO22		PAD_CTRL_PU_22k	/* USBO power en */
				>;
		};
		pinctrl_reset_moci: gpio_reset_moci {
			fsl,pins = <
				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	PAD_CTRL_PU_22k	/* RESET_MOCI control */
				>;
		};
		pinctrl_sd_cd: gpio_sd_cd {
			fsl,pins = <
				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	PAD_CTRL_NO	/* SD1 CD */
				>;
		};
		pinctrl_spi_cs1: spi_cs1 {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25	PAD_CTRL_NO	/* SPI1 cs */
				>;
		};
		pinctrl_spi_cs2: spi_cs2 {
			fsl,pins = <
				MX6QDL_PAD_EIM_RW__GPIO2_IO26		PAD_CTRL_NO	/* SPI2 cs */
				>;
		};
		pinctrl_touch_int_1: touch_int-1 {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL2__GPIO4_IO10		PAD_CTRL_HYS_PU /* STMPE811 interrupt */
			>;
		};
	};

	ipu1 {

		pinctrl_ipu1_t1: ipu1grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
				MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61                /* DE */
				MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61                /* HSync */
				MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61                /* VSync */
				MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
				MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
				MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
				MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
				MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
				MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
				MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
				MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
				MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
				MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
				MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
				MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
				MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
				MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
				MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
				MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
				MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
				MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
				MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
				MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
				MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
				MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
				MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
				MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
			>;
		};
		pinctrl_ipu1_t2: ipu1grp-t2 { /* parallel camera */
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0xb0b1
				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0xb0b1
				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0xb0b1
				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0xb0b1
				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0xb0b1
				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0xb0b1
				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0xb0b1
				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0xb0b1
				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0xb0b1
				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0xb0b1
				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0xb0b1
			>;
		};
	};

	ipu2 {

		pinctrl_ipu2_t1: ipu2grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xD1
				MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xD1
				MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xD1
				MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xD1
				MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xF9
				MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xF9
				MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xF9
				MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xF9
				MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xF9
				MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xF9
				MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xF9
				MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xF9
				MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xF9
				MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xF9
				MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xF9
				MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xF9
				MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xF9
				MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xF9
				MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xF9
				MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xF9
			>;
		};
	};

	uart1 {

		pinctrl_uart1_t1: uart1grp-t1 { /* DTE mode */
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
				MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
				MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
			>;
		};

		pinctrl_uart1_t2: uart1grp-t2 { /* Additional DTR, DSR, DCD */
			fsl,pins = <
				MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
				MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
				MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
			>;
		};
	};

	uart2 {

		pinctrl_uart2_t1: uart2grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA   0x1b0b1
				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA   0x1b0b1
			>;
		};

		pinctrl_uart2_t2: uart2grp-t2 { /* DTE mode */
			fsl,pins = <
				MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA   0x1b0b1
				MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA   0x1b0b1
				MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
				MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
			>;
		};
	};

	uart4 {
		pinctrl_uart4_t1: uart4grp-t1 { /* DTE mode */
			fsl,pins = <
				MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
				MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
			>;
		};
	};

	uart5 {
		pinctrl_uart5_t1: uart5grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
			>;
		};
		pinctrl_uart5_t2: uart5grp-t2 { /* DTE mode */
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
				MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
			>;
		};
	};

	usdhc1 {

		pinctrl_usdhc1_t1: usdhc1grp-t1 {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
				MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
				MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
				MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
				MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
				MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
			>;
		};
	};
};

&ldb {
	ipu_id = <1>;
	disp_id = <1>;
	ext_ref = <1>;
	mode = "spl1";
	sec_ipu_id = <1>;
	sec_disp_id = <1>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1_3>;
	status = "disabled";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2_2>;
	status = "disabled";
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3_1>;
	status = "disabled";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4_1>;
	status = "disabled";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif_2>;
	status = "disabled";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
#ifndef USE_UART_IN_DCE_MODE
	pinctrl-0 = <&pinctrl_uart1_t1 &pinctrl_uart1_t2>;
	fsl,dte-mode;
	fsl,uart-has-rtscts;
#else
	pinctrl-0 = <&pinctrl_uart1_1>;
#endif
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default";
#ifndef USE_UART_IN_DCE_MODE
	pinctrl-0 = <&pinctrl_uart2_t2>;
	fsl,dte-mode;
	fsl,uart-has-rtscts;
#else
	pinctrl-0 = <&pinctrl_uart2_t1>;
#endif
	status = "disabled";
};

&uart4 {
	pinctrl-names = "default";
#ifndef USE_UART_IN_DCE_MODE
	pinctrl-0 = <&pinctrl_uart4_t1>;
 	fsl,dte-mode;
#else
	pinctrl-0 = <&pinctrl_uart4_1>;
#endif
	status = "disabled";
};

&uart5 {
	pinctrl-names = "default";
#ifndef USE_UART_IN_DCE_MODE
	pinctrl-0 = <&pinctrl_uart5_t2>;
 	fsl,dte-mode;
#else
	pinctrl-0 = <&pinctrl_uart5_t1>;
#endif
	status = "disabled";
};

&usbh1 {
	vbus-supply = <&reg_usb_host_vbus>;
	status = "disabled";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg_2>;
	disable-over-current;
	status = "disabled";
};

/* MMC1 */
&usdhc1 {
	label = "MMC1";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1_t1 &pinctrl_mmc_cd>;
	cd-gpios = <&gpio4 20 0>;
	vmmc-supply = <&reg_3p3v>;
	bus-width = <8>;
	no-1-8-v;
	status = "disabled";
};

/* SD1 */
&usdhc2 {
	label = "SD1";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2_2 &pinctrl_sd_cd>;
	cd-gpios = <&gpio6 14 0>;
	vmmc-supply = <&reg_3p3v>;
	bus-width = <4>;
	no-1-8-v;
	status = "disabled";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3_1>;
	vmmc-supply = <&reg_3p3v>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};