1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
|
/*
* PHYTEC phyCORE-LPC3250 board
*
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "lpc32xx.dtsi"
/ {
model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
compatible = "phytec,phy3250", "nxp,lpc3250";
#address-cells = <1>;
#size-cells = <1>;
memory {
device_type = "memory";
reg = <0x80000000 0x4000000>;
};
regulators {
backlight_reg: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "backlight_reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio 5 4 0>;
enable-active-high;
regulator-boot-on;
};
lcd_reg: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "lcd_reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio 5 0 0>;
enable-active-high;
regulator-boot-on;
};
sd_reg: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "sd_reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio 5 5 0>;
enable-active-high;
};
};
leds {
compatible = "gpio-leds";
led0 { /* red */
gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
default-state = "off";
};
led1 { /* green */
gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
linux,default-trigger = "heartbeat";
};
};
};
&clcd {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 3 10 0>;
reset-gpio = <&gpio 3 2 0>;
dac-clk = "wspll";
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&i2c2 {
clock-frequency = <100000>;
};
&i2cusb {
clock-frequency = <100000>;
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
};
&key {
keypad,num-rows = <1>;
keypad,num-columns = <1>;
nxp,debounce-delay-ms = <3>;
nxp,scan-delay-ms = <34>;
linux,keymap = <0x00000002>;
status = "okay";
};
&mac {
phy-mode = "rmii";
use-iram;
};
/* Here, choose exactly one from: ohci, usbd */
&ohci /* &usbd */ {
transceiver = <&isp1301>;
status = "okay";
};
&sd {
wp-gpios = <&gpio 3 0 0>;
cd-gpios = <&gpio 3 1 0>;
cd-inverted;
bus-width = <4>;
vmmc-supply = <&sd_reg>;
status = "okay";
};
/* 64MB Flash via SLC NAND controller */
&slc {
status = "okay";
nxp,wdr-clks = <14>;
nxp,wwidth = <40000000>;
nxp,whold = <100000000>;
nxp,wsetup = <100000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <40000000>;
nxp,rhold = <66666666>;
nxp,rsetup = <100000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
read-only;
};
mtd1@00064000 {
label = "phy3250-uboot";
reg = <0x00064000 0x00190000>;
read-only;
};
mtd2@001f4000 {
label = "phy3250-ubt-prms";
reg = <0x001f4000 0x00010000>;
};
mtd3@00204000 {
label = "phy3250-kernel";
reg = <0x00204000 0x00400000>;
};
mtd4@00604000 {
label = "phy3250-rootfs";
reg = <0x00604000 0x039fc000>;
};
};
};
&ssp0 {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
cs-gpios = <&gpio 3 5 0>;
status = "okay";
eeprom: at25@0 {
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
pl022,interface = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
};
};
&tsc {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart5 {
status = "okay";
};
|
