1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
|
/*
* Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/mxc_dvfs.h>
#include "cpu_op-mx53.h"
/*!
* @file mach-mx5/cpu_op-mx53.c
*
* @brief This file contains the information about MX53 CPU working points.
*
* @ingroup MSL_MX53
*/
extern struct cpu_op *(*get_cpu_op)(int *op);
extern void (*set_num_cpu_op)(int num);
extern struct dvfs_op *(*get_dvfs_core_op)(int *wp);
static int num_cpu_op;
static struct cpu_op *cpu_op_table;
static struct dvfs_op *dvfs_core_setpoint;
static int num_dvfs_core_setpoint;
/* Place holder for dvfs_core setpoints for AEC parts */
static struct dvfs_op dvfs_core_setpoint_aec[] = {
{33, 0, 33, 10, 10, 0x08} }; /*800MHz*/
/* Place holder for dvfs_core setpoints for 1.2GHz parts */
static struct dvfs_op dvfs_core_setpoint_ces_1_2G[] = {
{33, 25, 33, 10, 10, 0x08}, /*1_2GHz*/
{30, 18, 33, 20, 10, 0x08}, /* 800MHz */
{25, 0, 33, 20, 10, 0x08}, /* 400MHz */
{28, 8, 33, 20, 30, 0x08}, /* 400MHZ, 133MHz */
{29, 0, 33, 20, 10, 0x08},}; /* 400MHZ, 50MHz. */
/* Place holder for dvfs_core setpoints for 1 GHz parts */
static struct dvfs_op dvfs_core_setpoint_ces[] = {
{33, 25, 33, 10, 10, 0x08}, /*1GHz*/
{30, 18, 33, 20, 10, 0x08}, /* 800MHz */
{25, 0, 33, 20, 10, 0x08}, /* 400MHz */
{28, 8, 33, 20, 30, 0x08}, /* 400MHz, 133MHz */
{29, 0, 33, 20, 10, 0x08},}; /* 400MHz, 50MHz. */
/* working point for auto*/
static struct cpu_op cpu_op_aec[] = {
{
.pll_rate = 800000000,
.cpu_rate = 800000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1100000,},
};
/* working point for consumer 1G*/
static struct cpu_op cpu_op_ces[] = {
{
.pll_rate = 1000000000,
.cpu_rate = 1000000000,
.pdf = 0,
.mfi = 10,
.mfd = 11,
.mfn = 5,
.cpu_podf = 0,
.cpu_voltage = 1250000,},
{
.pll_rate = 800000000,
.cpu_rate = 800000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1100000,},
{
.pll_rate = 800000000,
.cpu_rate = 400000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 1,
.cpu_voltage = 950000,},
};
/* working point for consumer 1.2G*/
static struct cpu_op cpu_op_ces_1_2g[] = {
{
.pll_rate = 1200000000,
.cpu_rate = 1200000000,
.pdf = 0,
.mfi = 12,
.mfd = 1,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1300000,},
{
.pll_rate = 800000000,
.cpu_rate = 800000000,
.pdf = 0,
.mfi = 8,
.mfd = 2,
.mfn = 1,
.cpu_podf = 0,
.cpu_voltage = 1100000,},
{
.pll_rate = 800000000,
.cpu_rate = 400000000,
.cpu_podf = 1,
.cpu_voltage = 950000,},
};
static struct dvfs_op *mx53_get_dvfs_core_table(int *wp)
{
/* Add 2 to num_cpu_wp to handle LPAPM mode transitions. */
*wp = num_dvfs_core_setpoint;
return dvfs_core_setpoint;
}
struct cpu_op *mx53_get_cpu_op(int *op)
{
*op = num_cpu_op;
return cpu_op_table;
}
void mx53_set_num_cpu_op(int num)
{
num_cpu_op = num;
return;
}
void mx53_cpu_op_init()
{
get_cpu_op = mx53_get_cpu_op;
set_num_cpu_op = mx53_set_num_cpu_op;
get_dvfs_core_op = mx53_get_dvfs_core_table;
}
void mx53_set_cpu_part_number(enum mx53_cpu_part_number part_num)
{
switch (part_num) {
case IMX53_CEC_1_2G:
cpu_op_table = cpu_op_ces_1_2g;
num_cpu_op = ARRAY_SIZE(cpu_op_ces_1_2g);
dvfs_core_setpoint = dvfs_core_setpoint_ces_1_2G;
num_dvfs_core_setpoint =
ARRAY_SIZE(dvfs_core_setpoint_ces_1_2G);
break;
case IMX53_CEC:
cpu_op_table = cpu_op_ces;
num_cpu_op = ARRAY_SIZE(cpu_op_ces);
dvfs_core_setpoint = dvfs_core_setpoint_ces;
num_dvfs_core_setpoint =
ARRAY_SIZE(dvfs_core_setpoint_ces);
break;
case IMX53_AEC:
default:
cpu_op_table = cpu_op_aec;
num_cpu_op = ARRAY_SIZE(cpu_op_aec);
dvfs_core_setpoint = dvfs_core_setpoint_aec;
num_dvfs_core_setpoint =
ARRAY_SIZE(dvfs_core_setpoint_aec);
break;
}
}
|
