path: root/arch/arm/mach-tegra/include/ap20/arapb_misc.h

/*
 * Copyright (c) 2009 NVIDIA Corporation.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * Neither the name of the NVIDIA Corporation nor the names of its contributors
 * may be used to endorse or promote products derived from this software
 * without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 */
//
// DO NOT EDIT - generated by simspec!
//

#ifndef ___ARAPB_MISC_H_INC_
#define ___ARAPB_MISC_H_INC_

// Reserved address 0 [0x0] 

// Reserved address 4 [0x4] 

// Register APB_MISC_PP_STRAPPING_OPT_A_0  
#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
#define APB_MISC_PP_STRAPPING_OPT_A_0_SECURE                    0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x3fc001f1)
#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x3fc001f1)
// read at power-on reset time from gmi_ad[15:12] strap pads.
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT                 _MK_SHIFT_CONST(26)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_RANGE                 29:26
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_WOFFSET                       0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// read at power-on reset time from gmi_hior strap pad
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(25)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  25:25
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)

// read at power-on reset time from gmi_hiow strap pad
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT                   _MK_SHIFT_CONST(24)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_RANGE                   24:24
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_WOFFSET                 0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_IROM                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_NOR                     _MK_ENUM_CONST(1)

// read at power-on reset time from {gmi_clk,gmi_adv_n} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       RSVD1
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD2                   _MK_ENUM_CONST(1)

// read at power-on reset time from gmi_ad[7:4] strap pads
// In emulation (HIDREV_MAJORREV==0), this field indicates the RAM type connected.
// For   QT (HIDREV_MINORREV==0): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
// For FPGA (HIDREV_MINORREV==1): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       RSVD1
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD2                   _MK_ENUM_CONST(1)


// Reserved address 12 [0xc] 

// Reserved address 16 [0x10] 

// Register APB_MISC_PP_TRISTATE_REG_A_0  
#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
#define APB_MISC_PP_TRISTATE_REG_A_0_SECURE                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0xc01bfff0)
#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT                        _MK_SHIFT_CONST(31)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_RANGE                        31:31
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_RANGE                      30:30
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_WOFFSET                    0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_INIT_ENUM                  TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_TRISTATE                   _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT                        _MK_SHIFT_CONST(29)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_RANGE                        29:29
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_RANGE                        28:28
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)


// Register APB_MISC_PP_TRISTATE_REG_B_0  
#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
#define APB_MISC_PP_TRISTATE_REG_B_0_SECURE                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0xffefee)
#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0xe6ffffef)
#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0xe6ffffef)
#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0xe6ffffef)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT                        _MK_SHIFT_CONST(31)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_RANGE                        31:31
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_RANGE                        30:30
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT                        _MK_SHIFT_CONST(29)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_RANGE                        29:29
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_RANGE                        0:0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_INIT_ENUM                    NORMAL
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_TRISTATE                     _MK_ENUM_CONST(1)


// Register APB_MISC_PP_TRISTATE_REG_C_0  
#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
#define APB_MISC_PP_TRISTATE_REG_C_0_SECURE                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)


// Register APB_MISC_PP_TRISTATE_REG_D_0  
#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
#define APB_MISC_PP_TRISTATE_REG_D_0_SECURE                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0xf1ff)
#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0xfdff)
#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0xfdff)
#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0xfdff)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_RANGE                        15:15
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_RANGE                       14:14
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_RANGE                        13:13
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)


// Register APB_MISC_PP_CONFIG_CTL_0  
#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
#define APB_MISC_PP_CONFIG_CTL_0_SECURE                         0x0
#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
//  0 = Disable ; 1 = Enable RTCK Daisychaining
#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)

//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)


// Register APB_MISC_PP_MISC_USB_OTG_0  
#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
#define APB_MISC_PP_MISC_USB_OTG_0_SECURE                       0x0
#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xc3ffffff)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xc3ffffff)
#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xc07fff29)
// Wake on Disconnect Enable (device mode)
// When enabled (1), USB PHY will wakeup
// from suspend on a disconnect event.
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)

// Wake on Connect Enable (device mode)
// When enabled (1), USB PHY will wakeup
// from suspend on a connect event.
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)

// B_SESS_END status from USB PHY.
// This field is the same as the field
// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)

// A_VBUS_VLD status from USB PHY.
// This field is the same as the field
// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)

// A_SESS_VLD status from USB PHY.
// This field is the same as the field
// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)

// Software_B_SESS_END status.
// Software should write the appropriate
// value (1/0) to set/unset the B_SESS_END status.
// This field is the same as the field
// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)

// Enable Software Controlled B_SESS_END.
// Software sets this bit to drive the
// value in  SW_B_SESS_END to the USB
// controller
// This field is the same as the field
// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)

// Software_A_VBUS_VLD status.
// Software should write the appropriate
// value (1/0) to set/unset the A_VBUS_VLD status.
// This field is the same as the field
// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)

// Enable Software Controlled A_VBUS_VLD.
// Software sets this bit to drive the
// value in SW_A_VBUS_VLD to the USB
// controller.
// This field is the same as the field
// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)

// Software_A_SESS_VLD status.
// Software should write the appropriate
// value (1/0) to set/unset the A_SESS_VLD status.
// This field is the same as the field
// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)

// Enable Software Controlled A_SESS_VLD.
// Software sets this bit to drive the
// value in SW_A_SESS_VLD to the USB
// controller.
// This field is the same as the field
// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)

// Suspend Set
// Software must write a 1 to this bit to put the USB PHY in
// suspend mode. Software should do this only after making sure that
// the USB is indeed in suspend mode. Setting this bit will stop the
// PHY clock. Software should write a 0 to clear it.
// NOTE: It is required that software generate a positive pulse on this
// bit to guarantee proper operation.
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)

// VBUS Change Interrupt Enable
// If set, an interrupt will be generated whenever
// A_SESS_VLD changes value. Software can read the
// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
// This field is the same as the field
// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)

// Software controlled OTG_ID.
// If SW_OTG_ID_EN = 1, then software needs to monitor
// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
// it can set this bit.
// This field is the same as the field
// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)

// Reserved
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// ID pullup enable.
// This field controls the internal pull-up to
// OTG_ID pin. Software should set this to
// 1 if using internal OTG_ID. If software
// is using a GPIO for OTG_ID, then it
// can write this to 0.
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)

//Suspend Clear
// Software must write a 1 to this bit to bring the PHY
// out of suspend mode. This is used when the software stops the PHY
// clock during suspend and then wants to initiate a resume. Software
// should also write 0 to clear it.
// NOTE: It is required that software generate a  positive pulse on this
// bit to guarantee proper operation.
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)

// Wake/resume on VBUS change change detect
// If enabled, the USB PHY will wake up whenever a
// change in A_SESS_VLD is detected.
// This should be set only when USB PHY is already
// suspended.
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)

// Resume/Clock valid interrupt enable
// If this bit is enabled, interrupt is generated
// whenever PHY clock becomes valid.
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)

// Wake on resume enable
// If this bit is enabled, USB PHY will wakeup from
// suspend whenever resume/reset signaling is
// detected on USB.
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)

// PHY clock valid status
// This bit is set whenever PHY clock becomes valid.
// It is cleared whenever PHY clock stops.
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)

// VBUS change detect
// This bit is set whenever a change in A_SESS_VLD
// is detected.
// Software can read the status of A_SESS_VLD from 
// A_SESS_VLD_STS2 bit.
// This field is the same as the field
// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)

// Loopback enable
// Not for normal software use
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)

// Real OTG_ID status from the USB PHY.
// This field is the same as the field
// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)

// Enable Software Controlled OTG_ID
// If using a GPIO for OTG_ID signal, then
// software can set this to 1 and write
// the value from the GPIO to the
// SW_OTG_ID bit in this register.
// This field is the same as the field
// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)

// USB PHY suspend status
// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
// NOTE: Software should not access any
// registers in USB controller when this
// bit is set.
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)

// Static General purpose input coming from ID pin
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)

// Polarity of the suspend signal going to USB PHY
// Software should not change this.
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)


// Reserved address 48 [0x30] 

// Reserved address 52 [0x34] 

// Reserved address 56 [0x38] 

// Reserved address 64 [0x40] 

// Reserved address 68 [0x44] 

// Reserved address 96 [0x60] 

// Register APB_MISC_PP_USB_PHY_PARAM_0  
#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
#define APB_MISC_PP_USB_PHY_PARAM_0_SECURE                      0x0
#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x18)
#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x18)
#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x18)
// Vbus_sense control
// Controls which VBUS sensor input is driven to the controller.
// 00: Use VBUS_WAKEUP.
// 01: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY if the PHY clock is available.
// Otherwise, use VBUS_WAKEUP.
// 10: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY
// 11: Use A_SESS_VLD output from the PHY
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(3)


// Reserved address 104 [0x68] 

// Reserved address 108 [0x6c] 

// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SECURE                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
// A_VBUS_VLD debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)

// A_VBUS_VLD software value.
// Software should write the appropriate
// value (1/0) to set/unset the A_VBUS_VLD status.
// This is only valid when A_VBUS_VLD_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)

// A_VBUS_VLD software enable.
// Enable Software Controlled A_VBUS_VLD.
// Software sets this bit to drive the
// value in A_VBUS_VLD_SW_VALUE to the USB
// controller.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)

// A_VBUS_VLD status.
// This is set to 1 whenever A_VBUS_VLD sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)

// A_VBUS_VLD change detect.
// This field is set by hardware whenever a change
// is detected in the value of A_VBUS_VLD.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)

// A_VBUS_VLD interrupt enable.
// If this field is set to 1, an interrupt is
// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)

// A_SESS_VLD debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)

// A_SESS_VLD software value.
// Software should write the appropriate
// value (1/0) to set/unset the A_SESS_VLD status.
// This is only valid when A_SESS_VLD_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)

// A_SESS_VLD software enable.
// Enable Software Controlled A_SESS_VLD.
// Software sets this bit to drive the
// value in A_SESS_VLD_SW_VALUE to the USB
// controller.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)

// A_SESS_VLD status.
// This is set to 1 whenever A_SESS_VLD sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)

// A_SESS_VLD change detect.
// This field is set by hardware whenever a change
// is detected in the value of A_SESS_VLD.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)

// A_SESS_VLD interrupt enable.
// If this field is set to 1, an interrupt is
// generated whenever A_SESS_VLD_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)

// B_SESS_VLD debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)

// B_SESS_VLD software value.
// Software should write the appropriate
// value (1/0) to set/unset the B_SESS_VLD status.
// This is only valid when B_SESS_VLD_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)

// B_SESS_VLD software enable.
// Enable Software Controlled B_SESS_VLD.
// Software sets this bit to drive the
// value in B_SESS_VLD_SW_VALUE to the USB
// controller.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)

// B_SESS_VLD status.
// This is set to 1 whenever B_SESS_VLD sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)

// B_SESS_VLD change detect.
// This field is set by hardware whenever a change
// is detected in the value of B_SESS_VLD.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)

// B_SESS_VLD interrupt enable.
// If this field is set to 1, an interrupt is
// generated whenever B_SESS_VLD_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)

// B_SESS_END debounce A/B select
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)

// B_SESS_END software value
// Software should write the appropriate
// value (1/0) to set/unset the B_SESS_END status.
// This is only valid when B_SESS_END_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)

// B_SESS_END software enable.
// Enable Software Controlled B_SESS_END
// Software sets this bit to drive the
// value in B_SESS_END_SW_VALUE to the USB
// controller.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)

// B_SESS_END status.
// This is set to 1 whenever B_SESS_END sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)

// B_SESS_END change detect.
// This field is set by hardware whenever a change
// is detected in the value of B_SESS_END.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)

// B_SESS_END interrupt enable
// If this field is set to 1, an interrupt is
// generated whenever B_SESS_END_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SECURE                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
// HS Tx to Tx inter-packet delay counter.
// Software should not change this.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// VDAT_DET debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)

// VDAT_DET software value.
// Software should write the appropriate
// value (1/0) to set/unset the VDAT_DET status.
// This is only valid when VDAT_DET_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)

// VDAT_DET software enable.
// Enable Software Controlled VDAT_DET.
// Software sets this bit to drive the
// value in VDAT_DET_SW_VALUE to the USB
// controller
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)

// VDAT_DET status.
// This is set to 1 whenever VDAT_DET sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)

// VDAT_DET change detect.
// This field is set by hardware whenever a change
// is detected in the value of VDAT_DET.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)

// VDAT_DET interrupt enable.
// If this field is set to 1, an interrupt is
// generated whenever VDAT_DET_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)

// VBUS_WAKEUP debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)

// VBUS_WAKEUP software value.
// Software should write the appropriate
// value (1/0) to set/unset the VBUS_WAKEUP status.
// This is only valid when VBUS_WAKEUP_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)

// VBUS_WAKEUP software enable.
// Enable Software Controlled VBUS_WAKEUP.
// Software sets this bit to drive the
// value in VBUS_WAKEUP_SW_VALUE to the USB
// controller.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)

// VBUS_WAKEUP status.
// This is set to 1 whenever VBUS_WAKEUP sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)

// VBUS_WAKEUP change detect.
// This field is set by hardware whenever a change
// is detected in the value of VBUS_WAKEUP.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)

// VBUS_WAKEUP interrupt enable
// If this field is set to 1, an interrupt is
// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)

// ID debounce A/B select.
// Selects between the two debounce values 
// UTMIP_BIAS_DEBOUNCE_A or
// UTMIP_BIAS_DEBOUNCE_B from the register
// UTMIP_DEBOUNCE_CFG0.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)

// ID software value.
// Software should write the appropriate
// value (1/0) to set/unset the ID status.
// This is only valid when ID_SW_EN is set.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)

// ID software enable.
// Enable Software Controlled ID.
// Software sets this bit to drive the
// value in ID_SW_VALUE to the USB
// controller
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)

// ID status.
// This is set to 1 whenever ID sensor
// output is 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)

// ID change detect.
// This field is set by hardware whenever a change
// is detected in the value of ID.
// software writes a 1 to clear it
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)

// ID interrupt enable.
// If this field is set to 1, an interrupt is
// generated whenever ID_CHG_DET is set to 1.
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)


// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SECURE                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0x7f)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
// A_SESS_VLD alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_RANGE                 6:6
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)

// B_SESS_VLD alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_RANGE                 5:5
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)

// ID alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)

// B_SESS_END alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT                 _MK_SHIFT_CONST(3)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_RANGE                 3:3
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SET                   _MK_ENUM_CONST(1)

// Static GPI alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)

// A_VBUS_VLD alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_RANGE                 1:1
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_WOFFSET                       0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SET                   _MK_ENUM_CONST(1)

// Vbus wakeup alternate status
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)


// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SECURE                  0x0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
// Reserved
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Reserved
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Reserved
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Reserved
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x2a22000)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xfff3f3ff)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xfff3f3ff)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xfff3f3ff)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RANGE                     31:30
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SDIO1                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RSVD1                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTE                     _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTA                     _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_OWR                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_TRACE                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SDIO4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SDIO4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SDIO4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RANGE                       9:8
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SPI1                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RSVD                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_UARTD                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_ULPI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPI4                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_OWR                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_ULPI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_ULPI                        _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0xa140a)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM                 _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_PCIE                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI4                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI4                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI4                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RANGE                       9:8
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_OWR                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD1                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD2                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD3                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_PCIE                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI4                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_HDMI                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD3                     _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD4                     _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_RANGE                       3:2
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_UARTD                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SPI4                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SFLASH                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_RANGE                       1:0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_UARTE                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SPI3                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SDIO4                       _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0xa8ca0000)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RANGE                       31:30
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SFLASH                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_RANGE                       29:28
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_IDE                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_NAND                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI_INT                     _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_GMI                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_GMI                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO2                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_GMI                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SPI4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_GMI                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SPI4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_TRACE                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_EMC_TEST1_DLL                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO2                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SDIO2                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_EMC_TEST0_DLL                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RANGE                       1:0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_I2C2                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD1                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD2                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD3                       _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0xffc00022)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_GMI                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_UARTA                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_PWM                 _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SPI2                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO2                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO2                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_PWM                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_PCIE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RANGE                       1:0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RSVD1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DAP5                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SDIO4                       _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RSVD3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_HDMI                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C3                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_NAND                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO2                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD3                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RANGE                      21:20
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_CRT                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD2                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD4                      _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_SECURE                      0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)

#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)


// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SECURE                   0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SECURE                   0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8865aa)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RANGE                 25:24
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SECURE                   0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xf3ffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xf3ffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xf3ffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 31:30
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RANGE                  25:24
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SECURE                   0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa1a55a8a)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RANGE                 27:26
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RSVD                  _MK_ENUM_CONST(3)

// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)

// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)


// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SECURE                   0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa008000a)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RANGE                  31:30
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RANGE                  29:28
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_INIT_ENUM                      PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RANGE                  27:26
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RANGE                  25:24
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RANGE                  23:22
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RANGE                  21:20
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RANGE                        19:18
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_WOFFSET                      0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_INIT_ENUM                    PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RSVD                 _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT                  _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RANGE                  17:16
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_WOFFSET                        0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_INIT_ENUM                      NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RSVD                   _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RANGE                 15:14
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RANGE                 13:12
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RANGE                 11:10
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RANGE                 9:8
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)

#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)


// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_SECURE                   0x0
#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
// Power is on in TDA/TDB partitions
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)

// Power is on in VE/MPE partitions
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)

// Power is on in CPU partition
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)


// Reserved address 1028 [0x404] 

// Reserved address 1032 [0x408] 

// Reserved address 1036 [0x40c] 

// Register APB_MISC_ASYNC_EMCPADEN_0  
#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
#define APB_MISC_ASYNC_EMCPADEN_0_SECURE                        0x0
#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
// outputs enable for EMC pads
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)

// inputs enable for EMC pads
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)


// Reserved address 1044 [0x414] 

// Reserved address 1048 [0x418] 

// Reserved address 1052 [0x41c] 

// Reserved address 1056 [0x420] 

// Reserved address 1060 [0x424] 

// Reserved address 1064 [0x428] 

// Register APB_MISC_ASYNC_VCLKCTRL_0  
#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
#define APB_MISC_ASYNC_VCLKCTRL_0_SECURE                        0x0
#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
// VCLK input enable
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)

// VCLK invert enable
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)


// Reserved address 1072 [0x430] 

// Reserved address 1076 [0x434] 

// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SECURE                         0x0
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APB_MISC_ASYNC_TVDACCNTL_0  
#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
#define APB_MISC_ASYNC_TVDACCNTL_0_SECURE                       0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
// Power down everything including the band-gap
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)

// Power down everything except the band-gap
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)

// Power down everything including the band-gap
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)

// Low power (sleep) mode. SHut down OUTR output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)

// Low power (sleep) mode. SHut down OUTG output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)

// Low power (sleep) mode. SHut down OUTB output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)

// Adjust threshold voltage of comparator inside DAC
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Turn bandgap averaging on/off
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)

// To adjust temp coeff
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Control bits for bandgap
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// For debugging. Selects internal analog output to be sent out of VREF pin
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Reserved for additional control
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Enable COMPOUTR output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)

// Enable COMPOUTG output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)

// Enable COMPOUTB output
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)

// Indicate load status
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)


// Register APB_MISC_ASYNC_TVDACSTATUS_0  
#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
#define APB_MISC_ASYNC_TVDACSTATUS_0_SECURE                     0x0
#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
// Channel R comparator output for auto-detect
// 0 = COMPINR > threshold
// 1 = COMPINR < threshold, or when POWERDOWN==1
// comparison threshold = 0.325V
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Channel G comparator output for auto-detect
// 0 = COMPING > threshold
// 1 = COMPING < threshold, or when POWERDOWN==1
// comparison threshold = 0.325V
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Channel B comparator output for auto-detect
// 0 = COMPINB > threshold
// 1 = COMPINB < threshold, or when POWERDOWN==1
// comparison threshold = 0.325V
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SECURE                  0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
// Data Input FIFO threshold
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// INPUT source for TVDAC
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)

// Override DAC DIN inputs
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)

// DIN override
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// AMPIN
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
//  This reflects status of all pending
//  interrupts which is valid as long as
//  the interrupt is not cleared even if the
//  interrupt is masked. A pending interrupt
//  can be cleared by writing a '1' to this
//  the corresponding interrupt status bit
//  in this register.
//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
//                                             //  (this is cleared on write)
//                                             //   0= interrupt not pending
//                                             //   1= interrupt pending
//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
//                                             //  (this is cleared on write)
//                                             //   0= interrupt not pending
//                                            //   1= interrupt pending
//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
//                                          //  (this is cleared on write)
//                                           //   0= interrupt not pending
//                                           //   1= interrupt pending
//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
//                                           //  (this is cleared on write)
//                                           //   0= interrupt not pending
//                                           //   1= interrupt pending
//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
//                                           //  (this is cleared on write)
//                                           //   0= interrupt not pending
//                                           //   1= interrupt pending
//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
//                                           //  (this is cleared on write)
//                                           //   0= interrupt not pending
//                                           //   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
#define APB_MISC_ASYNC_INT_STATUS_0_SECURE                      0x0
#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
// HGP7 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// HGP8 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// HGP9 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// HGP10 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// HGP11 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// HGP12 Interrupt Status
//  (this is cleared on write)
//   0= interrupt not pending
//   1= interrupt pending
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
// Setting bits in this register masked the
//  corresponding interrupt but does not
//  clear a pending interrupt and does not
//  prevent a pending interrupt to be generated.
//  Masking an interrupt also does not clear
//  a pending interrupt status and does not
//  a pending interrupt status to be generated.
//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
//                                           //   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
#define APB_MISC_ASYNC_INT_MASK_0_SECURE                        0x0
#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
// HGP7 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

// HGP8 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

// HGP9 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)

// HGP10 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

// HGP11 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)

// HGP12 Interrupt Mask   0= interrupt masked
//   1= interrupt not masked
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)


// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
//  These bits specify whether a pending interrupt 
//  is generated on falling edge or on rising edge 
//  of the corresponding input signal/event.
//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
//                                            //   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
#define APB_MISC_ASYNC_INT_POLARITY_0_SECURE                    0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
// HGP7 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

// HGP8 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

// HGP9 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)

// HGP10 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)

// HGP11 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)

// HGP12 Interrupt Polarity   0= falling edge interrupt
//   1= rising edge interrupt
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)


// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
//  These bits specify whether an interrupt 
//  is generated on an edge of a level type.
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SECURE                         0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
// HGP7 Interrupt Type   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

// HGP8 Interrupt Polarity   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

// HGP9 Interrupt Polarity   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)

// HGP10 Interrupt Polarity   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)

// HGP11 Interrupt Polarity   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)

// HGP12 Interrupt Polarity   0= Edge type
//   1= Level type
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)


// Register APB_MISC_GP_MODEREG_0  
#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
#define APB_MISC_GP_MODEREG_0_SECURE                    0x0
#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)

// LP-DDR Strap option bit 0.
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// LP-DDR Strap option bit 1.
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_HIDREV_0  
#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
#define APB_MISC_GP_HIDREV_0_SECURE                     0x0
#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x22017)
#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
// Chip ID family register. There maybe a new HIDFAM code
// added for MG20 products, this is still being descided.
#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)

// Chip ID major revision (0: Emulation, 1-15: Silicon)
#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)

// Chip ID
#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x20)
#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Reserved address 2056 [0x808] 

// Reserved address 2060 [0x80c] 

// Register APB_MISC_GP_ASDBGREG_0  
#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
#define APB_MISC_GP_ASDBGREG_0_SECURE                   0x0
#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
// Enables iddq (WARNING: Will functionally kill chip)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)

// Enables pullup
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)

// Enables pulldown
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)

// Enables debug mode
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)

// Enables performance monitor mode
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)

#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)

//  Obsolete previously used with host_pad_macros (jmoskal)
//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
//    enum ( DISABLE, ENABLE )
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)

// control timing characteristics for the compiled rams
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)

// control write timing characteristics for the compiled RAMDP
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// control write timing characteristics for the compiled RAMPDP
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// control write timing characteristics for the compiled RAMREG
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// control write timing characteristics for the compiled RAMSP
// ECO 385781, add reset to RAM_SVOP_SP
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Reserved address 2068 [0x814] 

// Register APB_MISC_GP_OBSCTRL_0  
#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
#define APB_MISC_GP_OBSCTRL_0_SECURE                    0x0
#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
// Module-level mux select for determining which debug signals to send out
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Observation module select
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PMC                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UAVP                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSI                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSICIL                        _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAY                       _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAYB                      _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DSI                   _MK_ENUM_CONST(4)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HDMI                  _MK_ENUM_CONST(5)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TVO                   _MK_ENUM_CONST(6)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CAR                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EMC                   _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_GR2D                  _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HOST1X                        _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MC                    _MK_ENUM_CONST(4)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MSELECT                       _MK_ENUM_CONST(5)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_STRAT12                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FUSE                  _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_KFUSE                 _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSITE                 _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CLIP                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_IDX                   _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SETUP                 _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VPE                   _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ALU                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ATRAST                        _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DWR                   _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FDC                   _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PSEQ                  _MK_ENUM_CONST(4)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_QRAST                 _MK_ENUM_CONST(5)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TEX                   _MK_ENUM_CONST(6)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEA                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEB                  _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEC                  _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UVDE                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EPP                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ISP                   _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VI                    _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PCIE2                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_AFI                   _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB2                  _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB3                  _MK_ENUM_CONST(2)

// Observation partition select
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AVP                  _MK_ENUM_CONST(1)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_PCX                  _MK_ENUM_CONST(5)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_ST                   _MK_ENUM_CONST(6)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(7)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(8)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(9)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(10)
#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_USX                  _MK_ENUM_CONST(11)

// Module internal mux select
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT                     _MK_SHIFT_CONST(24)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_FIELD                     (_MK_MASK_CONST(0x7f) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_RANGE                     30:24
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_WOFFSET                   0x0
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Observation bus enable
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)


// Register APB_MISC_GP_OBSDATA_0  
#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
#define APB_MISC_GP_OBSDATA_0_SECURE                    0x0
#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
// Observation port data.  This should be the same data that is going out on the observation bus.
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Reserved address 2080 [0x820] 

// Reserved address 2084 [0x824] 

// Reserved address 2088 [0x828] 

// Reserved address 2092 [0x82c] 

// Reserved address 2096 [0x830] 

// Reserved address 2100 [0x834] 

// Reserved address 2104 [0x838] 

// Reserved address 2108 [0x83c] 

// Reserved address 2112 [0x840] 

// Reserved address 2116 [0x844] 

// Reserved address 2120 [0x848] 

// Reserved address 2124 [0x84c] 

// Reserved address 2128 [0x850] 

// Reserved address 2132 [0x854] 

// Register APB_MISC_GP_ASDBGREG2_0  
#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
#define APB_MISC_GP_ASDBGREG2_0_SECURE                  0x0
#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
//Enable bypass of functional clock with test clock 8
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 9
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 10
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 11
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 12
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 13
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 14
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 15
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 16
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 17
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of functional clock with test clock 18
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)

//Enable bypass of sync Already in NV_car
//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
//            enum ( DISABLE, ENABLE )
//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
//      enum ( DISABLE, ENABLE )
//      enum ( DISABLE, ENABLE )
//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)


// Register APB_MISC_GP_ASDBGREG3_0  
#define APB_MISC_GP_ASDBGREG3_0                 _MK_ADDR_CONST(0x85c)
#define APB_MISC_GP_ASDBGREG3_0_SECURE                  0x0
#define APB_MISC_GP_ASDBGREG3_0_WORD_COUNT                      0x1
#define APB_MISC_GP_ASDBGREG3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
#define APB_MISC_GP_ASDBGREG3_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
// control write timing characteristics for the L1 idata and ddata rams
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_RANGE                   1:0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_WOFFSET                 0x0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// control write timing characteristics for the L1 itag  and dtag rams 
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT                    _MK_SHIFT_CONST(2)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_RANGE                    3:2
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_WOFFSET                  0x0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// control write timing characteristics for the L2 (SCU) data rams
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_RANGE                   5:4
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_WOFFSET                 0x0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// control write timing characteristics for the L2 (SCU) tag  rams 
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT                    _MK_SHIFT_CONST(6)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_RANGE                    7:6
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_WOFFSET                  0x0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// control write timing characteristics for the irams  
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_RANGE                     9:8
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_WOFFSET                   0x0
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_EMU_REVID_0  
#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
#define APB_MISC_GP_EMU_REVID_0_SECURE                  0x0
#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
// USED by emulators to indicate netlist #, 0 for silicon.
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST

// USED by emulators to indicate patch #, 0 for silicon.
#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH


// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SECURE                         0x0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
// used for emulation to determine test results. USE CPU specific registers below.
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
#define APB_MISC_GP_AOCFG1PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// AOCFG1 data pins high speed mode enable
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// AOCFG1 data pins schmidt enable
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// AOCFG1 data pins low power mode select
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
#define APB_MISC_GP_AOCFG2PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// AOCFG2 data pins high speed mode enable
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// AOCFG2 data pins schmidt enable
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// AOCFG2 data pins low power mode select
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
#define APB_MISC_GP_ATCFG1PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// ATCFG1 data pins high speed mode enable
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// ATCFG1 data pins schmidt enable
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// ATCFG1 data pins low power mode select
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
#define APB_MISC_GP_ATCFG2PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// ATCFG2 data pins high speed mode enable
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// ATCFG2 data pins schmidt enable
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// ATCFG2 data pins low power mode select
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// CDEV1CFG data pins high speed mode enable
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// CDEV1CFG data pins schmidt enable
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// CDEV1CFG data pins low power mode select
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// CDEV2CFG data pins high speed mode enable
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// CDEV2CFG data pins schmidt enable
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// CDEV2CFG data pins low power mode select
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// CSUSCFG data pins high speed mode enable
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// CSUSCFG data pins schmidt enable
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// CSUSCFG data pins low power mode select
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// DAP1CFG data pins high speed mode enable
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// DAP1CFG data pins schmidt enable
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// DAP1CFG data pins low power mode select
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// DAP2CFG data pins high speed mode enable
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// DAP2CFG data pins schmidt enable
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// DAP2CFG data pins low power mode select
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// DAP3CFG data pins high speed mode enable
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// DAP3CFG data pins schmidt enable
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// DAP3CFG data pins low power mode select
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// DAP4CFG data pins high speed mode enable
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// DAP4CFG data pins schmidt enable
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// DAP4CFG data pins low power mode select
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
#define APB_MISC_GP_DBGCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// DBGCFG data pins high speed mode enable
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// DBGCFG data pins schmidt enable
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// DBGCFG data pins low power mode select
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// LCDCFG1 data pins high speed mode enable
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// LCDCFG1 data pins schmidt enable
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// LCDCFG1 data pins low power mode select
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
// LCDCFG2 data pins high speed mode enable
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)

// LCDCFG2 data pins schmidt enable
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

// LCDCFG2 data pins low power mode select
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// SDIO2CFG data pins high speed mode enable
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// SDIO2CFG data pins schmidt enable
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// SDIO2CFG data pins low power mode select
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
#define APB_MISC_GP_SPICFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SPICFG data pins high speed mode enable
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SPICFG data pins schmidt enable
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SPICFG data pins low power mode select
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
#define APB_MISC_GP_UAACFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// UAACFG data pins high speed mode enable
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// UAACFG data pins schmidt enable
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// UAACFG data pins low power mode select
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
#define APB_MISC_GP_UABCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// UABCFG data pins high speed mode enable
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// UABCFG data pins schmidt enable
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// UABCFG data pins low power mode select
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
#define APB_MISC_GP_UART2CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// UART2CFG data pins high speed mode enable
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// UART2CFG data pins schmidt enable
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// UART2CFG data pins low power mode select
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
#define APB_MISC_GP_UART3CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// UART3CFG data pins high speed mode enable
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// UART3CFG data pins schmidt enable
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// UART3CFG data pins low power mode select
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
#define APB_MISC_GP_VICFG1PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// VICFG1 data pins high speed mode enable
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// VICFG1 data pins schmidt enable
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// VICFG1 data pins low power mode select
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
#define APB_MISC_GP_VICFG2PADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// VICFG2 data pins high speed mode enable
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// VICFG2 data pins schmidt enable
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// VICFG2 data pins low power mode select
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
//            enum ( DISABLE, ENABLE )
//        3       rw  CFG2TMC_XM2CFGA_RX_FT_REC_EN i=0x0   
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xffffc000)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xffffc070)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xffffc070)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xffffc070)
// XM2CFGA data pins bypass outbound flop enable
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_RANGE                    4:4
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)

// XM2CFGA data pins preemp enable
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT                    _MK_SHIFT_CONST(5)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE                    5:5
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_ENABLE                   _MK_ENUM_CONST(1)

// pad clk_sel  (ma bits get this value inverted in lpddr2 mode)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_RANGE                      6:6
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_WOFFSET                    0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    18:14
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    23:19
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       27:24
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:28
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
// XM2CFGD data pins schmidt enable
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_RANGE                       8:4
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_RANGE                       13:9
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    18:14
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    23:19
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       27:24
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:28
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
// XM2CFGD data pins schmidt enable
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_RANGE                       8:4
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_RANGE                       13:9
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    18:14
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    23:19
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       27:24
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:28
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SECURE                   0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xffffc002)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xffffc00e)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xffffc00e)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xffffc00e)
// XM2 bypass outbound flop enable
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_RANGE                        1:1
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_WOFFSET                      0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_ENABLE                       _MK_ENUM_CONST(1)

// preemp enable
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_RANGE                        2:2
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_WOFFSET                      0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_ENABLE                       _MK_ENUM_CONST(1)

// XM2CLKCFG bypass drvdn/up calibration 
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(3)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_RANGE                    3:3
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_WOFFSET                  0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        18:14
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(19)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        23:19
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   27:24
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(28)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:28
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2COMPPADCTRL_0  
#define APB_MISC_GP_XM2COMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
#define APB_MISC_GP_XM2COMPPADCTRL_0_SECURE                     0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_WORD_COUNT                         0x1
#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f008)
#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f0ff)
#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f0ff)
#define APB_MISC_GP_XM2COMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f0ff)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_RANGE                     3:0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_WOFFSET                   0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT                   _MK_MASK_CONST(0x8)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_RANGE                   4:4
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_WOFFSET                 0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT                     _MK_SHIFT_CONST(5)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_RANGE                     7:5
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_WOFFSET                   0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_RANGE                        16:12
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_WOFFSET                      0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_RANGE                        24:20
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_WOFFSET                      0x0
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2VTTGENPADCTRL_0  
#define APB_MISC_GP_XM2VTTGENPADCTRL_0                  _MK_ADDR_CONST(0x8d8)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SECURE                   0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WORD_COUNT                       0x1
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x5500)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0x7077701)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0x7077703)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x7077703)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_RANGE                    0:0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_WOFFSET                  0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// dummy pin
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_RANGE                     1:1
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_WOFFSET                   0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_RANGE                     10:8
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_WOFFSET                   0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT                   _MK_MASK_CONST(0x5)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_RANGE                      14:12
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_WOFFSET                    0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT                    _MK_MASK_CONST(0x5)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_RANGE                        18:16
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_WOFFSET                      0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_RANGE                        26:24
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_WOFFSET                      0x0
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_PADCTL_DFT_0  
#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8dc)
#define APB_MISC_GP_PADCTL_DFT_0_SECURE                         0x0
#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
// Enable pin-shorting for tester mode pin-shorting
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)

// Select which pins are used for test-mode observe
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_SDIO1CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO1CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_SDIO1CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_SDIO1CFGPADCTRL_0                   _MK_ADDR_CONST(0x8e0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SECURE                    0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WORD_COUNT                        0x1
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_RANGE                     2:2
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_WOFFSET                   0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_RANGE                   3:3
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_WOFFSET                 0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_RANGE                       5:4
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_WOFFSET                     0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_RANGE                  16:12
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_WOFFSET                        0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_RANGE                  24:20
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_WOFFSET                        0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CFGCPADCTRL2_0  
#define APB_MISC_GP_XM2CFGCPADCTRL2_0                   _MK_ADDR_CONST(0x8e4)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SECURE                    0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WORD_COUNT                        0x1
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x8080042)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xf0f00ff)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0xf0f00ff)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xf0f00ff)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_RANGE                        0:0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_WOFFSET                      0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)

// XM2CFGD data pins bypass outbound flop enable
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_RANGE                   1:1
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_WOFFSET                 0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)

// XM2CFGD data pins preemp enable
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_RANGE                   2:2
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_WOFFSET                 0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_RANGE                  3:3
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT                 _MK_SHIFT_CONST(4)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_RANGE                 4:4
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_WOFFSET                       0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_ENABLE                        _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT                  _MK_SHIFT_CONST(5)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_RANGE                  5:5
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_ENABLE                 _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT                   _MK_SHIFT_CONST(6)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_RANGE                   6:6
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_WOFFSET                 0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT                  _MK_SHIFT_CONST(7)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_RANGE                  7:7
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT                    _MK_SHIFT_CONST(16)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_RANGE                    19:16
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_WOFFSET                  0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT                  _MK_MASK_CONST(0x8)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT                     _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_RANGE                     27:24
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_WOFFSET                   0x0
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT                   _MK_MASK_CONST(0x8)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_XM2CFGDPADCTRL2_0  
#define APB_MISC_GP_XM2CFGDPADCTRL2_0                   _MK_ADDR_CONST(0x8e8)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SECURE                    0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WORD_COUNT                        0x1
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x2)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0x7777000f)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0x7777000f)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0x7777000f)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_RANGE                        0:0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_WOFFSET                      0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)

// XM2CFGD data pins bypass outbound flop enable
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_RANGE                   1:1
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_WOFFSET                 0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)

// XM2CFGD data pins preemp enable
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_RANGE                   2:2
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_WOFFSET                 0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)

#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_RANGE                  3:3
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)

//delay trim for byte 0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(16)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_RANGE                  18:16
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

//delay trim for byte 1
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_RANGE                  22:20
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

//delay trim for byte 2
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_RANGE                  26:24
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

//delay trim for byte 3
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(28)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_RANGE                  30:28
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_WOFFSET                        0x0
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CRTCFGPADCTRL_0  //        0       rw  CFG2TMC_CRTCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_CRTCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_CRTCFGPADCTRL_0                     _MK_ADDR_CONST(0x8ec)
#define APB_MISC_GP_CRTCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_CRTCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DDCCFGPADCTRL_0  //        0       rw  CFG2TMC_DDCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_DDCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_DDCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_DDCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_GMACFGPADCTRL_0  //        0       rw  CFG2TMC_GMACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_GMACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_GMACFGPADCTRL_0                     _MK_ADDR_CONST(0x8f4)
#define APB_MISC_GP_GMACFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_GMBCFGPADCTRL_0  //        0       rw  CFG2TMC_GMBCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_GMBCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_GMBCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f8)
#define APB_MISC_GP_GMBCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMBCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_GMCCFGPADCTRL_0  //        0       rw  CFG2TMC_GMCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_GMCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_GMCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8fc)
#define APB_MISC_GP_GMCCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_GMDCFGPADCTRL_0  //        0       rw  CFG2TMC_GMDCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_GMDCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_GMDCFGPADCTRL_0                     _MK_ADDR_CONST(0x900)
#define APB_MISC_GP_GMDCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMDCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_GMECFGPADCTRL_0  //        0       rw  CFG2TMC_GMECFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_GMECFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_GMECFGPADCTRL_0                     _MK_ADDR_CONST(0x904)
#define APB_MISC_GP_GMECFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_GMECFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_OWRCFGPADCTRL_0  //        0       rw  CFG2TMC_OWRCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_OWRCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_OWRCFGPADCTRL_0                     _MK_ADDR_CONST(0x908)
#define APB_MISC_GP_OWRCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_OWRCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_UADCFGPADCTRL_0  //        0       rw  CFG2TMC_UDACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
//            enum ( DISABLE, ENABLE )
//        1       rw  CFG2TMC_UDACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
//            enum ( DISABLE, ENABLE )
#define APB_MISC_GP_UADCFGPADCTRL_0                     _MK_ADDR_CONST(0x90c)
#define APB_MISC_GP_UADCFGPADCTRL_0_SECURE                      0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_WORD_COUNT                  0x1
#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
#define APB_MISC_GP_UADCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
// SDIO3CFG data pins high speed mode enable
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_RANGE                 2:2
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_WOFFSET                       0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)

// SDIO3CFG data pins schmidt enable
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_RANGE                       3:3
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_WOFFSET                     0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)

// SDIO3CFG data pins low power mode select
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_RANGE                   5:4
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_WOFFSET                 0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_RANGE                      16:12
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_WOFFSET                    0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_RANGE                      24:20
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_WOFFSET                    0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_RANGE                 29:28
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_RANGE                 31:30
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0  
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0                    _MK_ADDR_CONST(0x920)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SECURE                     0x0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WORD_COUNT                         0x1
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
// used for emulation to determine test results.
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_RANGE                       31:0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_WOFFSET                     0x0
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0  
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x924)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
// used for emulation to determine test results.
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0  
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x928)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SECURE                    0x0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
// used for emulation to determine test results.
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_RANGE                     31:0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_WOFFSET                   0x0
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DEV_PRESENT0_0  
#define APB_MISC_GP_DEV_PRESENT0_0                      _MK_ADDR_CONST(0x92c)
#define APB_MISC_GP_DEV_PRESENT0_0_SECURE                       0x0
#define APB_MISC_GP_DEV_PRESENT0_0_WORD_COUNT                   0x1
#define APB_MISC_GP_DEV_PRESENT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_DEV_PRESENT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_RANGE                       0:0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_RANGE                     1:1
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_RANGE                     2:2
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_RANGE                     3:3
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_RANGE                     4:4
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT                        _MK_SHIFT_CONST(5)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_RANGE                        5:5
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_RANGE                      6:6
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT                      _MK_SHIFT_CONST(7)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_RANGE                      7:7
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_RANGE                       8:8
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT                     _MK_SHIFT_CONST(9)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_RANGE                     9:9
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT                 _MK_SHIFT_CONST(10)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_RANGE                 10:10
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_WOFFSET                       0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT                    _MK_SHIFT_CONST(11)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_RANGE                    11:11
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT                 _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_RANGE                 12:12
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_WOFFSET                       0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_RANGE                        13:13
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT                 _MK_SHIFT_CONST(14)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_RANGE                 14:14
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_WOFFSET                       0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_RANGE                        15:15
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_RANGE                        16:16
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_RANGE                       17:17
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_RANGE                       18:18
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT                        _MK_SHIFT_CONST(19)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_RANGE                        19:19
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT                    _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_RANGE                    20:20
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT                   _MK_SHIFT_CONST(21)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_RANGE                   21:21
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT                      _MK_SHIFT_CONST(22)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_RANGE                      22:22
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT                    _MK_SHIFT_CONST(23)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_RANGE                    23:23
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT                    _MK_SHIFT_CONST(24)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_RANGE                    24:24
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT                    _MK_SHIFT_CONST(25)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_RANGE                    25:25
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT                       _MK_SHIFT_CONST(26)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_RANGE                       26:26
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_RANGE                       27:27
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_RANGE                       28:28
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT                       _MK_SHIFT_CONST(29)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_RANGE                       29:29
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_RANGE                        30:30
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT                       _MK_SHIFT_CONST(31)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_RANGE                       31:31
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DEV_PRESENT1_0  
#define APB_MISC_GP_DEV_PRESENT1_0                      _MK_ADDR_CONST(0x930)
#define APB_MISC_GP_DEV_PRESENT1_0_SECURE                       0x0
#define APB_MISC_GP_DEV_PRESENT1_0_WORD_COUNT                   0x1
#define APB_MISC_GP_DEV_PRESENT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_DEV_PRESENT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_RANGE                    0:0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT                    _MK_SHIFT_CONST(1)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_RANGE                    1:1
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_RANGE                  2:2
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_RANGE                       3:3
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_RANGE                      4:4
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT                      _MK_SHIFT_CONST(5)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_RANGE                      5:5
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_RANGE                      6:6
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT                      _MK_SHIFT_CONST(7)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_RANGE                      7:7
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT                      _MK_SHIFT_CONST(8)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_RANGE                      8:8
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT                      _MK_SHIFT_CONST(9)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_RANGE                      9:9
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_RANGE                      10:10
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT                        _MK_SHIFT_CONST(11)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_RANGE                        11:11
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT                     _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_RANGE                     12:12
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_RANGE                        13:13
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_RANGE                       14:14
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_RANGE                       15:15
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_RANGE                       16:16
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT                      _MK_SHIFT_CONST(17)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_RANGE                      17:17
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_RANGE                       18:18
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_RANGE                       19:19
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_RANGE                      20:20
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT                      _MK_SHIFT_CONST(21)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_RANGE                      21:21
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT                      _MK_SHIFT_CONST(22)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_RANGE                      22:22
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT                      _MK_SHIFT_CONST(23)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_RANGE                      23:23
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_RANGE                      24:24
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT                       _MK_SHIFT_CONST(25)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_RANGE                       25:25
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT                   _MK_SHIFT_CONST(26)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_RANGE                   26:26
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT                      _MK_SHIFT_CONST(27)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_RANGE                      27:27
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_RANGE                        28:28
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT                       _MK_SHIFT_CONST(29)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_RANGE                       29:29
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT                    _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_RANGE                    30:30
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT                        _MK_SHIFT_CONST(31)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_RANGE                        31:31
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DEV_PRESENT2_0  
#define APB_MISC_GP_DEV_PRESENT2_0                      _MK_ADDR_CONST(0x934)
#define APB_MISC_GP_DEV_PRESENT2_0_SECURE                       0x0
#define APB_MISC_GP_DEV_PRESENT2_0_WORD_COUNT                   0x1
#define APB_MISC_GP_DEV_PRESENT2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_DEV_PRESENT2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_RANGE                       0:0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT                       _MK_SHIFT_CONST(1)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_RANGE                       1:1
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_RANGE                        2:2
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_RANGE                       3:3
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_RANGE                       4:4
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT                       _MK_SHIFT_CONST(5)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_RANGE                       5:5
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_RANGE                       6:6
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT                        _MK_SHIFT_CONST(7)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_RANGE                        7:7
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_RANGE                        8:8
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT                        _MK_SHIFT_CONST(9)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_RANGE                        9:9
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT                        _MK_SHIFT_CONST(10)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_RANGE                        10:10
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT                        _MK_SHIFT_CONST(11)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_RANGE                        11:11
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_RANGE                       12:12
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT                       _MK_SHIFT_CONST(13)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_RANGE                       13:13
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_RANGE                        14:14
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_RANGE                       15:15
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_RANGE                       16:16
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT                        _MK_SHIFT_CONST(17)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_RANGE                        17:17
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_RANGE                        18:18
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_RANGE                       19:19
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_RANGE                  20:20
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT                  _MK_SHIFT_CONST(21)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_RANGE                  21:21
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_RANGE                  22:22
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT                 _MK_SHIFT_CONST(23)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_RANGE                 23:23
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_WOFFSET                       0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT                    _MK_SHIFT_CONST(24)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_RANGE                    24:24
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(25)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_RANGE                      25:25
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(26)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_RANGE                      26:26
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT                      _MK_SHIFT_CONST(27)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_RANGE                      27:27
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT                   _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_RANGE                   28:28
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT                   _MK_SHIFT_CONST(29)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_RANGE                   29:29
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT                   _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_RANGE                   30:30
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(31)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_RANGE                        31:31
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DEV_PRESENT3_0  
#define APB_MISC_GP_DEV_PRESENT3_0                      _MK_ADDR_CONST(0x938)
#define APB_MISC_GP_DEV_PRESENT3_0_SECURE                       0x0
#define APB_MISC_GP_DEV_PRESENT3_0_WORD_COUNT                   0x1
#define APB_MISC_GP_DEV_PRESENT3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_DEV_PRESENT3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_RANGE                        0:0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_RANGE                        1:1
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_RANGE                        2:2
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_RANGE                        3:3
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_RANGE                        4:4
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(5)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_RANGE                        5:5
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_RANGE                        6:6
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT                        _MK_SHIFT_CONST(7)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_RANGE                        7:7
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT                        _MK_SHIFT_CONST(8)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_RANGE                        8:8
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT                        _MK_SHIFT_CONST(9)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_RANGE                        9:9
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT                        _MK_SHIFT_CONST(10)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_RANGE                        10:10
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT                        _MK_SHIFT_CONST(11)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_RANGE                        11:11
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_RANGE                        12:12
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT                       _MK_SHIFT_CONST(13)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_RANGE                       13:13
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_RANGE                       14:14
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_RANGE                       15:15
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT                       _MK_SHIFT_CONST(16)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_RANGE                       16:16
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT                       _MK_SHIFT_CONST(17)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_RANGE                       17:17
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT                       _MK_SHIFT_CONST(18)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_RANGE                       18:18
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT                   _MK_SHIFT_CONST(19)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_RANGE                   19:19
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT                  _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_RANGE                  20:20
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT                        _MK_SHIFT_CONST(21)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_RANGE                        21:21
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT                   _MK_SHIFT_CONST(22)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_RANGE                   22:22
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT                    _MK_SHIFT_CONST(23)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_RANGE                    23:23
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_RANGE                       24:24
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT                    _MK_SHIFT_CONST(25)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_RANGE                    25:25
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_WOFFSET                  0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT                        _MK_SHIFT_CONST(26)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_RANGE                        26:26
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT                  _MK_SHIFT_CONST(27)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_RANGE                  27:27
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_RANGE                       28:28
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT                        _MK_SHIFT_CONST(29)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_RANGE                        29:29
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_RANGE                     30:30
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT                       _MK_SHIFT_CONST(31)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_RANGE                       31:31
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_DEV_PRESENT4_0  
#define APB_MISC_GP_DEV_PRESENT4_0                      _MK_ADDR_CONST(0x93c)
#define APB_MISC_GP_DEV_PRESENT4_0_SECURE                       0x0
#define APB_MISC_GP_DEV_PRESENT4_0_WORD_COUNT                   0x1
#define APB_MISC_GP_DEV_PRESENT4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_RESET_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_GP_DEV_PRESENT4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_RANGE                     0:0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_RANGE                     1:1
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_RANGE                     2:2
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_RANGE                     3:3
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_RANGE                      4:4
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT                      _MK_SHIFT_CONST(5)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_RANGE                      5:5
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT                       _MK_SHIFT_CONST(6)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_RANGE                       6:6
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_RANGE                       7:7
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT                       _MK_SHIFT_CONST(8)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_RANGE                       8:8
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT                       _MK_SHIFT_CONST(9)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_RANGE                       9:9
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT                       _MK_SHIFT_CONST(10)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_RANGE                       10:10
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT                       _MK_SHIFT_CONST(11)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_RANGE                       11:11
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT                       _MK_SHIFT_CONST(12)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_RANGE                       12:12
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT                       _MK_SHIFT_CONST(13)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_RANGE                       13:13
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_RANGE                       14:14
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_RANGE                       15:15
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_WOFFSET                     0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_RANGE                      16:16
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT                      _MK_SHIFT_CONST(17)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_RANGE                      17:17
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_RANGE                      18:18
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT                      _MK_SHIFT_CONST(19)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_RANGE                      19:19
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT                      _MK_SHIFT_CONST(20)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_RANGE                      20:20
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT                      _MK_SHIFT_CONST(21)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_RANGE                      21:21
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_RANGE                  22:22
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_WOFFSET                        0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT                        _MK_SHIFT_CONST(23)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_RANGE                        23:23
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_RANGE                        24:24
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_WOFFSET                      0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT                     _MK_SHIFT_CONST(25)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_RANGE                     25:25
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT                     _MK_SHIFT_CONST(26)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_RANGE                     26:26
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_WOFFSET                   0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT                      _MK_SHIFT_CONST(27)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_RANGE                      27:27
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_WOFFSET                    0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT                   _MK_SHIFT_CONST(28)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_RANGE                   28:28
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT                   _MK_SHIFT_CONST(29)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_RANGE                   29:29
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_WOFFSET                 0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_RANGE                 30:30
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_WOFFSET                       0x0
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_ADDR_0  
#define APB_MISC_GP_L2EMU_ADDR_0                        _MK_ADDR_CONST(0x940)
#define APB_MISC_GP_L2EMU_ADDR_0_SECURE                         0x0
#define APB_MISC_GP_L2EMU_ADDR_0_WORD_COUNT                     0x1
#define APB_MISC_GP_L2EMU_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
#define APB_MISC_GP_L2EMU_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
// 256-bit aligned cache address
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_FIELD                       (_MK_MASK_CONST(0x7fff) << APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT)
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_RANGE                       14:0
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_WOFFSET                     0x0
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_BE_0  
#define APB_MISC_GP_L2EMU_BE_0                  _MK_ADDR_CONST(0x944)
#define APB_MISC_GP_L2EMU_BE_0_SECURE                   0x0
#define APB_MISC_GP_L2EMU_BE_0_WORD_COUNT                       0x1
#define APB_MISC_GP_L2EMU_BE_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_BE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_BE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_BE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
// byte enables
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_RANGE                   31:0
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_WOFFSET                 0x0
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT                 _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_INIT_ENUM                       -1


// Register APB_MISC_GP_L2EMU_DATA0_0  
#define APB_MISC_GP_L2EMU_DATA0_0                       _MK_ADDR_CONST(0x948)
#define APB_MISC_GP_L2EMU_DATA0_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA0_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 0
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT)
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA1_0  
#define APB_MISC_GP_L2EMU_DATA1_0                       _MK_ADDR_CONST(0x94c)
#define APB_MISC_GP_L2EMU_DATA1_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA1_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 1
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT)
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA2_0  
#define APB_MISC_GP_L2EMU_DATA2_0                       _MK_ADDR_CONST(0x950)
#define APB_MISC_GP_L2EMU_DATA2_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA2_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 2
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT)
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA3_0  
#define APB_MISC_GP_L2EMU_DATA3_0                       _MK_ADDR_CONST(0x954)
#define APB_MISC_GP_L2EMU_DATA3_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA3_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 3
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT)
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA4_0  
#define APB_MISC_GP_L2EMU_DATA4_0                       _MK_ADDR_CONST(0x958)
#define APB_MISC_GP_L2EMU_DATA4_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA4_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 4
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT)
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA5_0  
#define APB_MISC_GP_L2EMU_DATA5_0                       _MK_ADDR_CONST(0x95c)
#define APB_MISC_GP_L2EMU_DATA5_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA5_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA5_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA5_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 5
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT)
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA6_0  
#define APB_MISC_GP_L2EMU_DATA6_0                       _MK_ADDR_CONST(0x960)
#define APB_MISC_GP_L2EMU_DATA6_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA6_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA6_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA6_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 6
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT)
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_DATA7_0  
#define APB_MISC_GP_L2EMU_DATA7_0                       _MK_ADDR_CONST(0x964)
#define APB_MISC_GP_L2EMU_DATA7_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_DATA7_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_DATA7_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_GP_L2EMU_DATA7_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// data word 7
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT)
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_RANGE                     31:0
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_READ_0  
#define APB_MISC_GP_L2EMU_READ_0                        _MK_ADDR_CONST(0x968)
#define APB_MISC_GP_L2EMU_READ_0_SECURE                         0x0
#define APB_MISC_GP_L2EMU_READ_0_WORD_COUNT                     0x1
#define APB_MISC_GP_L2EMU_READ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_READ_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_GP_L2EMU_READ_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
// trigger cache line read
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT)
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_RANGE                       0:0
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_WOFFSET                     0x0
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_GP_L2EMU_WRITE_0  
#define APB_MISC_GP_L2EMU_WRITE_0                       _MK_ADDR_CONST(0x96c)
#define APB_MISC_GP_L2EMU_WRITE_0_SECURE                        0x0
#define APB_MISC_GP_L2EMU_WRITE_0_WORD_COUNT                    0x1
#define APB_MISC_GP_L2EMU_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_READ_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_GP_L2EMU_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
// trigger cache line write
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT)
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_RANGE                     0:0
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_WOFFSET                   0x0
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
//
// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
//
// With a 12MHz input from PLL_U, the default setting of 
// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
#define APB_MISC_UTMIP_PLL_CFG0_0_SECURE                        0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
// LOCK_ENABLE input of USB_PHY PLL.
// Normally only used during test. See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// LOCKSEL[5:0] input of USB_PHY PLL.
// Used in test modes only. See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// VCOMULTBY2 control of the UTMIP PHY PLL.
// Recommended setting is on. Additional divide by 2 on the 
// VCO feedback. Which is setting the bit to 1. See cell spec.
//
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
// 0x0 is not allowed. See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// NDIV[7:0] input of USB_PHY PLL. 
// This is the feedback divider on the VCO feedback. 
// 0x0 is not allowed. See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// PDIV[2:0] input of the USB_PHY PLL.
// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
// See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// PDIVRST of the UTMIP PHY PLL.
// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
// See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Selects which of the eight 60MHz clock phases to produce at the output 
// of the USB PHY PLL. This is for a test mode. See cell specification.
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
#define APB_MISC_UTMIP_PLL_CFG1_0_SECURE                        0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force USB_PHY PLL pll_active input on. 
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force USB_PHY PLL pll_enable input on. 
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Force PLL_U into power up.
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// SETUP[8:0] input of USB_PHY PLL.
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Controls the wait time to enable PLL_U when coming out of suspend or reset.
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
#define APB_MISC_UTMIP_XCVR_CFG0_0_SECURE                       0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x20202500)
#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
// SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// HS slew rate control. The two LSBs.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// FS slew rate control.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// LS rising slew rate control.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// LS falling slew rate control.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Internal loopback inside XCVR cell. Used for IOBIST.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Enable HS termination.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Force PD input into power up. 
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Force PD2 input into power up.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Force PDZI input into power up.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Disconnect method on the usb transceiver pad
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT                       _MK_SHIFT_CONST(20)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_RANGE                       20:20
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Low speed bias selection method for usb transceiver pad
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT                  _MK_SHIFT_CONST(21)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_RANGE                  21:21
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_WOFFSET                        0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Most significant bits of SETUP.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT                   _MK_SHIFT_CONST(22)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_FIELD                   (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_RANGE                   24:22
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_WOFFSET                 0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Most significant bits of HS_SLEW.
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT                  _MK_SHIFT_CONST(25)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_FIELD                  (_MK_MASK_CONST(0x7f) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_RANGE                  31:25
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_WOFFSET                        0x0
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT                        _MK_MASK_CONST(0x10)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
#define APB_MISC_UTMIP_BIAS_CFG0_0_SECURE                       0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffffff)
// HS squelch detector level.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// HS disconnect detector level.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// HS chirp detector level.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// SessionEnd detector level.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Vbus detector level.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Power down bias circuit.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Power down OTG circuit.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Active 1.5K pullup control offset.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Active termination control offset.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// See GPI_SEL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// See IDDIG_SEL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// See IDPD_SEL.
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT                       _MK_SHIFT_CONST(24)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_RANGE                       24:24
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_WOFFSET                     0x0
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
#define APB_MISC_UTMIP_HSRX_CFG0_0_SECURE                       0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
// Require 4 sync pattern transitions (01) instead of 3
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Sync pattern detection needs 3 consecutive samples instead of 4
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Based on incoming edges and current sampling position, adjust phase
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Retime the path. 
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Pass through the feedback, do not block it.
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// When in Chirp Mode, allow chirp rx data through
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Do not declare underrun errors
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Do not declare overrun errors until overflow of FIFO
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Depth of elastic input store
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Number of cycles of idle to declare IDLE. 
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Do not strip incoming data
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Limit the delay of the squelch at EOP time
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// The number of (edges-1) needed to move the sampling point
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Realign the inertia counters on a new packet
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Allow consecutive ups and downs on the bits, debug only, set to 0.
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Keep the stay alive pattern on active
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
#define APB_MISC_UTMIP_HSRX_CFG1_0_SECURE                       0x0
#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
// Allow Keep Alive packets 
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// How long to wait before start of sync launches RxActive
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SECURE                     0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
// Give up on packet if a long sequence of J 
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Enable the reset of the state machine on extended SE0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// 4 bits of of SEO should exceed the time limit
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Require a full sync pattern to declare the data received
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Limit the number of bit times a K can last
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Number of K bits in question
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Only look for transitioning out of EOP
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Do not allow >= dribble bits 
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Do not allow <= dribble bits
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Filter SE1
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// One SE1, don't allow dribble
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SECURE                     0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Whether full speed uses debouncing
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Only look for a KK pattern, instead of KJKK
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Allow for large dribble in full speed mode
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Allow for large dribble in low  speed mode
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Only for this number of 60MHz of SEO and Idle to end packet
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Number of SEO clock cycles to block bit extraction
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Phase count on which LS bits are extracted
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Number of clock cycle of LS stable
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Assumes line state filtering table is inclusive, not exclusive
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
#define APB_MISC_UTMIP_TX_CFG0_0_SECURE                         0x0
#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x10200)
#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
// Do not sent SYNC or EOP
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// No encoding, static programming
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// No bit stuffing, static programming
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Sof when OpMode 2 -- not likely, for Chirp
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Sof when OpMode 3 -- perhaps, when sending controller made packets
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// SIE, not macrocell, detects LineState change to resume
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// output enable turns on  1 cycle before
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// output enable turns off 1 cycle after
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Disable high speed disconnect
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Only check during EOP
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Allow SOP to be source of transmit error stuffing
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// output enable turns on  1/2 cycle before
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// output enable turns off 1/2 cycle after 
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// output enable sends an initial J before sync pattern
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
#define APB_MISC_UTMIP_MISC_CFG0_0_SECURE                       0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
// Use combinational terminations or synced through CLKXTAL
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Use free running terminations at all time
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Ignore free running terminations, even when no clock
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Don't use free running terminations during suspend.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Determines if all signal need to be stable to not change a config.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Number of cycles of crystal clock of signal not changing to consider stable.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Force DM pulldown active.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force DP pulldown active.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force DM pullup active.      
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force DP pullup active.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force HS termination active.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Force HS termination inactive.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// Force HS clock always on.
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Force error insertion into RX path. (Used for IOBIST.)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)

// Don't block changes for 4ms when going from LS to FS (should not happen)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// Suspend exit requires edge or simply a value...
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Use DP/DM as obs bus
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Select DP/DM obs signals
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
#define APB_MISC_UTMIP_MISC_CFG1_0_SECURE                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x40198024)
#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
// Bit 0: 0: 0xa5 -> treat as KeepAlive 
//        1: treat as regular packet 
// Bit 1: 0: Turn on FS EOP detection
//        1: Turn off FS EOP detection
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// WRONG! This should be 1ms -> 0x50
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)

// 5 us / (1/19.2MHz) = 96 / 16 = 6
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)

// 0: Use FS filtering on line state when XcvrSel=3
// 1: Use LS filtering on line state when XcvrSel=3
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Use neg edge sync for linestate
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Bypass LineState reclocking logic
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Selects whether to enable the crystal clock in the module.
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                 _MK_SHIFT_CONST(30)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                 30:30
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                       0x0
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SECURE                   0x0
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
// simulation value -- Used for interrupts
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// simulation value -- Used for interrupts
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SECURE                   0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
// Power down charger circuit
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
#define APB_MISC_UTMIP_SPARE_CFG0_0_SECURE                      0x0
#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
// Spare register bits
// 0: HS_RX_IPG_ERROR_ENABLE
// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
// 3: FUSE_SETUP_SEL. Select between regular CFG value and JTAG values for UX_SETUP
// 31 to 4: Reserved
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536


// Register APB_MISC_UTMIP_XCVR_CFG1_0  // UTMIP transceiver cell configuration register 1
#define APB_MISC_UTMIP_XCVR_CFG1_0                      _MK_ADDR_CONST(0xa38)
#define APB_MISC_UTMIP_XCVR_CFG1_0_SECURE                       0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x822a)
#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
#define APB_MISC_UTMIP_XCVR_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
// Force PDDISC input into power down. (Overrides FORCE_PDDISC_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_RANGE                   0:0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_WOFFSET                 0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Force PDDISC input into power up.
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT                     _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_RANGE                     1:1
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Force PDCHRP input input into power down. (Overrides FORCE_PDCHRP_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE                   2:2
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_WOFFSET                 0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)

// Force PDCHRP input into power up.
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT                     _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_RANGE                     3:3
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Force PDDR input input into power down. (Overrides FORCE_PDDR_POWERUP.)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(4)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_RANGE                     4:4
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Force PDDR input into power up.
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT                       _MK_SHIFT_CONST(5)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_RANGE                       5:5
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)

// Encoded value to use on TCTRL when software override is enabled, 0 to 16 only
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(6)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_RANGE                     10:6
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Use a software override on TCTRL instead of automatic bias control
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(11)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_RANGE                     11:11
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Encoded value to use on RCTRL when software override is enabled, 0 to 16 only
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(12)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_RANGE                     16:12
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Use a software override on RCTRL instead of automatic bias control
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(17)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_RANGE                     17:17
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_WOFFSET                   0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)

// Range adjusment on terminations.
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                      _MK_SHIFT_CONST(18)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_RANGE                      21:18
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_WOFFSET                    0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Spare bits for usb transceiver pad ECO.
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT                       _MK_SHIFT_CONST(22)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_RANGE                       23:22
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_WOFFSET                     0x0
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_BIAS_CFG1_0  // UTMIP Bias cell configuration register 1
#define APB_MISC_UTMIP_BIAS_CFG1_0                      _MK_ADDR_CONST(0xa3c)
#define APB_MISC_UTMIP_BIAS_CFG1_0_SECURE                       0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x2a)
#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fff)
#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fff)
#define APB_MISC_UTMIP_BIAS_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fff)
// Force PDTRK input into power down. (Overrides FORCE_PDTRK_POWERUP.)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_RANGE                    0:0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Force PDTRK input into power up.
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT                      _MK_SHIFT_CONST(1)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_RANGE                      1:1
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_WOFFSET                    0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT                    _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)

// Force VBUS_WAKEUP input into power down.
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(2)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_RANGE                    2:2
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Control the BIAS cell power down lag. The lag should be 20us. For a Xtal clock of 13MHz it should be set a 5. 
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT                 _MK_SHIFT_CONST(3)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_RANGE                 7:3
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_WOFFSET                       0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT                       _MK_MASK_CONST(0x5)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)

// Debouncer time scaling, factor-1 to slow down debouncing by. So 0 is 1, 1 is 2, etc.
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT                  _MK_SHIFT_CONST(8)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_RANGE                  13:8
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_WOFFSET                        0x0
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)


// Register APB_MISC_UTMIP_BIAS_STS0_0  // UTMIP Bias cell status register 0
#define APB_MISC_UTMIP_BIAS_STS0_0                      _MK_ADDR_CONST(0xa40)
#define APB_MISC_UTMIP_BIAS_STS0_0_SECURE                       0x0
#define APB_MISC_UTMIP_BIAS_STS0_0_WORD_COUNT                   0x1
#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
#define APB_MISC_UTMIP_BIAS_STS0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
// Thermal encoding output from USB bias pad. 
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_RANGE                    15:0
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)

// Thermal encoding output from USB bias pad. 
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT                    _MK_SHIFT_CONST(16)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_RANGE                    31:16
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_WOFFSET                  0x0
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)


// Register APB_MISC_DAS_DAP_CTRL_SEL_0  
#define APB_MISC_DAS_DAP_CTRL_SEL_0                     _MK_ADDR_CONST(0xc00)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_SECURE                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_READ_MASK                   _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_RANGE                    31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RANGE                      30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RANGE                      29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_RANGE                  4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_WOFFSET                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)


// Register APB_MISC_DAS_DAP_CTRL_SEL  
#define APB_MISC_DAS_DAP_CTRL_SEL                       _MK_ADDR_CONST(0xc00)
#define APB_MISC_DAS_DAP_CTRL_SEL_SECURE                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_WORD_COUNT                    0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_VAL                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_MASK                    _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_READ_MASK                     _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_WRITE_MASK                    _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT                      _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_RANGE                      31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SLAVE                      _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_MASTER                     _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT                        _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RANGE                        30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_WOFFSET                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_TX                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RX                   _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT                        _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RANGE                        29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_WOFFSET                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RX                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_TX                   _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT                    _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_RANGE                    4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC1                     _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC2                     _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC3                     _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP1                     _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP2                     _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP3                     _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP4                     _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP5                     _MK_ENUM_CONST(20)


// Register APB_MISC_DAS_DAP_CTRL_SEL_1  
#define APB_MISC_DAS_DAP_CTRL_SEL_1                     _MK_ADDR_CONST(0xc04)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_SECURE                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_READ_MASK                   _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_RANGE                    31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RANGE                      30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RANGE                      29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_RANGE                  4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_WOFFSET                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)


// Register APB_MISC_DAS_DAP_CTRL_SEL_2  
#define APB_MISC_DAS_DAP_CTRL_SEL_2                     _MK_ADDR_CONST(0xc08)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_SECURE                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_READ_MASK                   _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_RANGE                    31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RANGE                      30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RANGE                      29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_RANGE                  4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_WOFFSET                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)


// Register APB_MISC_DAS_DAP_CTRL_SEL_3  
#define APB_MISC_DAS_DAP_CTRL_SEL_3                     _MK_ADDR_CONST(0xc0c)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_SECURE                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_READ_MASK                   _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_RANGE                    31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RANGE                      30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RANGE                      29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_RANGE                  4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_WOFFSET                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)


// Register APB_MISC_DAS_DAP_CTRL_SEL_4  
#define APB_MISC_DAS_DAP_CTRL_SEL_4                     _MK_ADDR_CONST(0xc10)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_SECURE                      0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_READ_MASK                   _MK_MASK_CONST(0xe000001f)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_RANGE                    31:31
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_WOFFSET                  0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)

//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RANGE                      30:30
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)

//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RANGE                      29:29
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_WOFFSET                    0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)

//DAP selection bits to select one of the three DACs or one of the five DAPs
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_RANGE                  4:0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_WOFFSET                        0x0
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)


// Reserved address 3092 [0xc14] 

// Reserved address 3096 [0xc18] 

// Reserved address 3100 [0xc1c] 

// Reserved address 3104 [0xc20] 

// Reserved address 3108 [0xc24] 

// Reserved address 3112 [0xc28] 

// Reserved address 3116 [0xc2c] 

// Reserved address 3120 [0xc30] 

// Reserved address 3124 [0xc34] 

// Reserved address 3128 [0xc38] 

// Reserved address 3132 [0xc3c] 

// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0  
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0                   _MK_ADDR_CONST(0xc40)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SECURE                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WORD_COUNT                        0x1
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_READ_MASK                         _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
//These bits are to control the selection of sdata2 input for DACs. 
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_RANGE                      31:28
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of sdata1 input for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_RANGE                      27:24
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of bit clock and fsync for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_RANGE                 3:0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_WOFFSET                       0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)


// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL  
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL                     _MK_ADDR_CONST(0xc40)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SECURE                      0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WORD_COUNT                  0x1
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_VAL                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_MASK                  _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_READ_MASK                   _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WRITE_MASK                  _MK_MASK_CONST(0xff00000f)
//These bits are to control the selection of sdata2 input for DACs. 
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT                        _MK_SHIFT_CONST(28)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_RANGE                        31:28
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_WOFFSET                      0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP1                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP2                 _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP3                 _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP4                 _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP5                 _MK_ENUM_CONST(4)

//These bits are to control the selection of sdata1 input for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT                        _MK_SHIFT_CONST(24)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_RANGE                        27:24
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_WOFFSET                      0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP1                 _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP2                 _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP3                 _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP4                 _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP5                 _MK_ENUM_CONST(4)

//These bits are to control the selection of bit clock and fsync for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT                   _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_RANGE                   3:0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_WOFFSET                 0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP1                    _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP2                    _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP3                    _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP4                    _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP5                    _MK_ENUM_CONST(4)


// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1  
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1                   _MK_ADDR_CONST(0xc44)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SECURE                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WORD_COUNT                        0x1
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_READ_MASK                         _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
//These bits are to control the selection of sdata2 input for DACs. 
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_RANGE                      31:28
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of sdata1 input for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_RANGE                      27:24
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of bit clock and fsync for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_RANGE                 3:0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_WOFFSET                       0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)


// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2  
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2                   _MK_ADDR_CONST(0xc48)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SECURE                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WORD_COUNT                        0x1
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_VAL                         _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_READ_MASK                         _MK_MASK_CONST(0xff00000f)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
//These bits are to control the selection of sdata2 input for DACs. 
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_RANGE                      31:28
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of sdata1 input for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_RANGE                      27:24
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_WOFFSET                    0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)

//These bits are to control the selection of bit clock and fsync for DACs.
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_RANGE                 3:0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_WOFFSET                       0x0
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)


// Reserved address 3148 [0xc4c] 

// Reserved address 3152 [0xc50] 

// Reserved address 3156 [0xc54] 

// Reserved address 3160 [0xc58] 

// Reserved address 3164 [0xc5c] 

// Reserved address 3168 [0xc60] 

// Reserved address 3172 [0xc64] 

// Reserved address 3176 [0xc68] 

// Reserved address 3180 [0xc6c] 

// Reserved address 3184 [0xc70] 

// Reserved address 3188 [0xc74] 

// Reserved address 3192 [0xc78] 

// Reserved address 3196 [0xc7c] 

//
// REGISTER LIST
//
#define LIST_ARAPB_MISC_REGS(_op_) \
_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
_op_(APB_MISC_PP_CONFIG_CTL_0) \
_op_(APB_MISC_PP_MISC_USB_OTG_0) \
_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
_op_(APB_MISC_ASYNC_EMCPADEN_0) \
_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
_op_(APB_MISC_ASYNC_INT_STATUS_0) \
_op_(APB_MISC_ASYNC_INT_MASK_0) \
_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
_op_(APB_MISC_GP_MODEREG_0) \
_op_(APB_MISC_GP_HIDREV_0) \
_op_(APB_MISC_GP_ASDBGREG_0) \
_op_(APB_MISC_GP_OBSCTRL_0) \
_op_(APB_MISC_GP_OBSDATA_0) \
_op_(APB_MISC_GP_ASDBGREG2_0) \
_op_(APB_MISC_GP_ASDBGREG3_0) \
_op_(APB_MISC_GP_EMU_REVID_0) \
_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
_op_(APB_MISC_GP_XM2COMPPADCTRL_0) \
_op_(APB_MISC_GP_XM2VTTGENPADCTRL_0) \
_op_(APB_MISC_GP_PADCTL_DFT_0) \
_op_(APB_MISC_GP_SDIO1CFGPADCTRL_0) \
_op_(APB_MISC_GP_XM2CFGCPADCTRL2_0) \
_op_(APB_MISC_GP_XM2CFGDPADCTRL2_0) \
_op_(APB_MISC_GP_CRTCFGPADCTRL_0) \
_op_(APB_MISC_GP_DDCCFGPADCTRL_0) \
_op_(APB_MISC_GP_GMACFGPADCTRL_0) \
_op_(APB_MISC_GP_GMBCFGPADCTRL_0) \
_op_(APB_MISC_GP_GMCCFGPADCTRL_0) \
_op_(APB_MISC_GP_GMDCFGPADCTRL_0) \
_op_(APB_MISC_GP_GMECFGPADCTRL_0) \
_op_(APB_MISC_GP_OWRCFGPADCTRL_0) \
_op_(APB_MISC_GP_UADCFGPADCTRL_0) \
_op_(APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0) \
_op_(APB_MISC_GP_DEV_PRESENT0_0) \
_op_(APB_MISC_GP_DEV_PRESENT1_0) \
_op_(APB_MISC_GP_DEV_PRESENT2_0) \
_op_(APB_MISC_GP_DEV_PRESENT3_0) \
_op_(APB_MISC_GP_DEV_PRESENT4_0) \
_op_(APB_MISC_GP_L2EMU_ADDR_0) \
_op_(APB_MISC_GP_L2EMU_BE_0) \
_op_(APB_MISC_GP_L2EMU_DATA0_0) \
_op_(APB_MISC_GP_L2EMU_DATA1_0) \
_op_(APB_MISC_GP_L2EMU_DATA2_0) \
_op_(APB_MISC_GP_L2EMU_DATA3_0) \
_op_(APB_MISC_GP_L2EMU_DATA4_0) \
_op_(APB_MISC_GP_L2EMU_DATA5_0) \
_op_(APB_MISC_GP_L2EMU_DATA6_0) \
_op_(APB_MISC_GP_L2EMU_DATA7_0) \
_op_(APB_MISC_GP_L2EMU_READ_0) \
_op_(APB_MISC_GP_L2EMU_WRITE_0) \
_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
_op_(APB_MISC_UTMIP_TX_CFG0_0) \
_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
_op_(APB_MISC_UTMIP_SPARE_CFG0_0) \
_op_(APB_MISC_UTMIP_XCVR_CFG1_0) \
_op_(APB_MISC_UTMIP_BIAS_CFG1_0) \
_op_(APB_MISC_UTMIP_BIAS_STS0_0) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL_0) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL_1) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL_2) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL_3) \
_op_(APB_MISC_DAS_DAP_CTRL_SEL_4) \
_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0) \
_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL) \
_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1) \
_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_APB_MISC   0x00000000
#define BASE_ADDRESS_APB_MISC_PP        0x00000000
#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
#define BASE_ADDRESS_APB_MISC_GP        0x00000800
#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
#define BASE_ADDRESS_APB_MISC_DAS       0x00000c00

//
// ARAPB_MISC REGISTER BANKS
//

#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
#define APB_MISC_PP2_FIRST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
#define APB_MISC_PP2_LAST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
#define APB_MISC_PP3_FIRST_REG 0x0070 // APB_MISC_PP_USB_PHY_VBUS_SENSORS_0
#define APB_MISC_PP3_LAST_REG 0x00b0 // APB_MISC_PP_PULLUPDOWN_REG_E_0
#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
#define APB_MISC_ASYNC1_FIRST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
#define APB_MISC_ASYNC1_LAST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
#define APB_MISC_ASYNC2_FIRST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
#define APB_MISC_ASYNC2_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
#define APB_MISC_ASYNC3_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
#define APB_MISC_ASYNC3_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
#define APB_MISC_GP1_LAST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
#define APB_MISC_GP2_FIRST_REG 0x0818 // APB_MISC_GP_OBSCTRL_0
#define APB_MISC_GP2_LAST_REG 0x081c // APB_MISC_GP_OBSDATA_0
#define APB_MISC_GP3_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
#define APB_MISC_GP3_LAST_REG 0x090c // APB_MISC_GP_UADCFGPADCTRL_0
#define APB_MISC_GP4_FIRST_REG 0x0920 // APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0
#define APB_MISC_GP4_LAST_REG 0x096c // APB_MISC_GP_L2EMU_WRITE_0
#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
#define APB_MISC_UTMIP0_LAST_REG 0x0a40 // APB_MISC_UTMIP_BIAS_STS0_0
#define APB_MISC_DAS0_FIRST_REG 0x0c00 // APB_MISC_DAS_DAP_CTRL_SEL_0
#define APB_MISC_DAS0_LAST_REG 0x0c10 // APB_MISC_DAS_DAP_CTRL_SEL_4
#define APB_MISC_DAS1_FIRST_REG 0x0c40 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0
#define APB_MISC_DAS1_LAST_REG 0x0c48 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2

#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

#endif // ifndef ___ARAPB_MISC_H_INC_