blob: cc270e654cb53864cb57835e39d83465dfedfd53 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
/*
* arch/arm/mach-tegra/include/mach/usb-hcd.h
*
* HCD platform data definitions
*
* Copyright (C) 2009 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef __MACH_TEGRA_USB_HCD_H
#define __MACH_TEGRA_USB_HCD_H
#include "nvcommon.h"
#include "nvrm_gpio.h"
#include "nvodm_query.h"
#include "nvddk_usbphy.h"
enum {
ID_PIN_CABLE_ID = 1,
ID_PIN_GPIO,
};
struct tegra_hcd_platform_data {
NvU32 instance;
unsigned int id_detect;
int gpio_nr;
bool otg_mode;
bool fast_wakeup;
NvU32 powerClientId;
NvU32 vBusPowerRail;
/* USB PHY power rail. Tegra has integrated UTMI (USB transciver
* macrocell interface) PHY on USB controllers 0 and 2. These 2 PHYs
* have its own rails.
*/
NvU32 phyPowerRail;
NvDdkUsbPhyHandle hUsbPhy;
struct work_struct work;
};
#endif
|