path: root/arch/arm/plat-mxc/include/mach/mvf.h

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#ifndef __MACH_MVF_H__
#define __MACH_MVF_H__

/*
 * IROM
 */
#define MVF_IROM_BASE_ADDR		0x0
#define MVF_IROM_SIZE			(SZ_64K + SZ_32K)
#define BOOT_ROM_BASE_ADDR		MVF_IROM_BASE_ADDR
#define ROMCP_SIZE			MVF_IROM_SIZE
/* TZASC */
#define MVF_TZASC_BASE_ADDR		0x40010000

/*
 * AHCI SATA
 */
#define MVF_SATA_BASE_ADDR		0x10000000

/*
 * NFC
 */
#define MVF_NFC_AXI_BASE_ADDR	0xF7FF0000	/* NAND flash AXI */
#define MVF_NFC_AXI_SIZE		SZ_64K

/* CPU Memory Map */
#define DDRMC0_BASE_ADDR		0x80000000
#define DDRMC0_END_ADDR		0xDFFFFFFF
#define DDRMC1_BASE_ADDR		0xE0000000
#define DDRMC1_END_ADDR		0xEFFFFFFF
#define OCRAM_ARB_BASE_ADDR		0x3F000000
#define OCRAM_ARB_END_ADDR		0x3F3FFFFF
#define IRAM_BASE_ADDR			OCRAM_ARB_BASE_ADDR

/*
 * IRAM
 */
#define MVF_IRAM_BASE_ADDR	0x3F000000	/* internal ram */
#define MVF_IRAM_PARTITIONS	2
#define MVF_IRAM_SIZE		(MVF_IRAM_PARTITIONS * SZ_256K)	/* 512KB */


#ifdef CONFIG_MXC_VPU_IRAM
#define VPU_IRAM_SIZE  0x100000
#else
#define VPU_IRAM_SIZE 0
#endif

#define ANADIG_BASE_ADDR	0x40050000
/*
 * Graphics Memory of GPU
 */
/*
#define MVF_IPU_CTRL_BASE_ADDR	0x18000000
#define MVF_GPU2D_BASE_ADDR		0x20000000
#define MVF_GPU_BASE_ADDR		0x30000000
#define MVF_GPU_GMEM_BASE_ADDR	0xF8020000
#define MVF_GPU_GMEM_SIZE	SZ_256K

#define MVF_DEBUG_BASE_ADDR		0x40000000
#define MVF_DEBUG_SIZE		SZ_1M
#define MVF_ETB_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00001000)
#define MVF_ETM_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00002000)
#define MVF_TPIU_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00003000)
#define MVF_CTI0_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00004000)
#define MVF_CTI1_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00005000)
#define MVF_CTI2_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00006000)
#define MVF_CTI3_BASE_ADDR		(MVF_DEBUG_BASE_ADDR + 0x00007000)
#define MVF_CORTEX_DBG_BASE_ADDR	(MVF_DEBUG_BASE_ADDR + 0x00008000)
*/
/*
 * SPBA global module enabled #0
 */
/*
#define MVF_SPBA0_BASE_ADDR		0x50000000
#define MVF_SPBA0_SIZE		SZ_1M

#define MVF_ESDHC1_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00004000)
#define MVF_ESDHC2_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00008000)
#define MVF_UART3_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x0000C000)
#define MVF_ECSPI1_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x00010000)
#define MVF_SSI2_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x00014000)
#define MVF_ESAI_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x00018000)
#define MVF_ESDHC3_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00020000)
#define MVF_ESDHC4_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00024000)
#define MVF_SPDIF_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x00028000)
#define MVF_ASRC_BASE_ADDR		(MVF_SPBA0_BASE_ADDR + 0x0002C000)
#define MVF_ATA_DMA_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00030000)
#define MVF_SLIM_DMA_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00034000)
#define MVF_HSI2C_DMA_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x00038000)
#define MVF_SPBA_CTRL_BASE_ADDR	(MVF_SPBA0_BASE_ADDR + 0x0003C000)
*/
/*
 * AIPS-Lite 0
 */
#define MVF_AIPS0_BASE_ADDR	0x40000000
#define MVF_AIPS0_SIZE		(0x70000)


#define MVF_MSCM_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00001000)
#define MVF_SCUGIC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00002000)
#define MVF_INTD_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00003000)
#define MVF_L2C_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00006000)
#define MVF_NIC0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00008000)
#define MVF_AHBTZASC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00010000)
#define MVF_CSU_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00017000)
#define MVF_DMA0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00018000)
#define MVF_DMA0TCD_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00019000)
#define MVF_SEMA4_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0001D000)
#define MVF_FLEXBUS_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0001E000)
#define MVF_FLEXCAN0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00021000)
#define MVF_DMAMUX0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00024000)
#define MVF_DMAMUX1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00025000)
#define MVF_UART0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00027000)
#define MVF_UART1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00028000)
#define MVF_UART2_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00029000)
#define MVF_UART3_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0002A000)

#define MVF_DSPI0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0002C000)
#define MVF_DSPI1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0002D000)
#define MVF_SAI0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0002F000)
#define MVF_SAI1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00030000)
#define MVF_SAI2_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00031000)
#define MVF_SAI3_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00032000)

#define MVF_CRC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00033000)
#define MVF_USB1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00034000)
#define MVF_PDB_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00036000)
#define MVF_PIT_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00037000)
#define MVF_FTM0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00038000)
#define MVF_FTM1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00039000)
#define MVF_ADC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0003B000)
#define MVF_TCON0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0003D000)
#define MVF_WDOG1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0003E000)
#define MVF_LPTMR_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00040000)
#define MVF_RLE_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00042000)
#define MVF_MLB_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00043000)
#define MVF_QUADSPI0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00044000)
#define MVF_IOMUXC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00048000)
#define MVF_GPIOA_MUX_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00049000)
#define MVF_GPIOB_MUX_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0004A000)
#define MVF_GPIOC_MUX_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0004B000)
#define MVF_GPIOD_MUX_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0004C000)
#define MVF_GPIOE_MUX_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0004D000)
#define MVF_ANATOP_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00050000)
#define MVF_SCSC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00052000)
#define MVF_DCU0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00058000)
#define MVF_ASRC_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00060000)
#define MVF_SPDIF_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00061000)
#define MVF_ESAI_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00062000)
#define MVF_ESAIBIFIFO_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00063000)
#define MVF_EWM_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00065000)
#define MVF_I2C0_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00066000)
#define MVF_I2C1_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x00067000)
#define MVF_WKUP_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0006A000)

#define MVF_CCM_BASE_ADDR	(MVF_AIPS0_BASE_ADDR + 0x0006B000)
#define MVF_GPC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR + 0x0006C000)
#define MVF_VREG_BASE_ADDR	(MVF_AIPS1_BASE_ADDR + 0x0006D000)
#define MVF_SRC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR + 0x0006E000)
#define MVF_CMU_BASE_ADDR	(MVF_AIPS1_BASE_ADDR + 0x0006F000)

#define L2_BASE_ADDR		MVF_L2C_BASE_ADDR

#define MVF_USBC0_CTRL_BASE_ADDR	0x40034800
#define MVF_USBC1_CTRL_BASE_ADDR	0x400B4800
#define MVF_USBC0_PHY_BASE_ADDR		0x40034818
#define MVF_USBC1_PHY_BASE_ADDR		0x400B4818
#define MVF_USBC0_BASE_ADDR		0x40034000
#define MVF_USBC1_BASE_ADDR		0x400B4000
#define MVF_USBPHY0_BASE_ADDR		0x40050800
#define MVF_USBPHY1_BASE_ADDR		0x40050B00

#define MVF_MSCM_INT_ROUTER_BASE	(MVF_MSCM_BASE_ADDR + 0x800)


/*
 * AIPS 1
 */
#define MVF_AIPS1_BASE_ADDR		0x40080000
#define MVF_AIPS1_SIZE			(0x80000)

#define MVF_DAP_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00087000)
#define MVF_DBG_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00088000)
#define MVF_PMU_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00089000)
#define MVF_ETM_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x0008C000)

#define MVF_DMA1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00098000)
#define MVF_DMA1TCD_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x00099000)
#define MVF_DMAMUX2_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A1000)
#define MVF_DMAMUX3_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A2000)
#define MVF_OTP_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A5000)
#define MVF_SNVS_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A7000)
#define MVF_WDOGSNVS_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A8000)
#define MVF_UART4_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000A9000)
#define MVF_UART5_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AB000)
#define MVF_DSPI2_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AC0000)
#define MVF_DSPI3_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AD0000)

#define MVF_MMDC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000AE000)
#define MVF_ESDHC0_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B1000)
#define MVF_ESDHC1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B2000)
#define MVF_OTG1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B4000)
#define MVF_FTM2_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B8000)
#define MVF_FTM3_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000B9000)
#define MVF_ADC1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BB000)
#define MVF_TCON1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BD000)
#define MVF_SEGLCD_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000BE000)
#define MVF_QUADSPI1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C4000)
#define MVF_VADC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C7000)
#define MVF_VDEC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C8000)
#define MVF_VIU3_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000C9000)
#define MVF_DAC0_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CC000)
#define MVF_DAC1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CD000)
#define MVF_OPENVG_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000CF000)
#define MVF_MAC0_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D0000)
#define MVF_MAC1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D1000)
#define MVF_FLEXCAN1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D4000)
#define MVF_DCU1_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000D8000)
#define MVF_NFC_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E0000)
#define MVF_I2C2_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E6000)
#define MVF_I2C3_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E7000)
#define MVF_L2SWITCH_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000E8000)
#define MVF_CAAM_BASE_ADDR	(MVF_AIPS1_BASE_ADDR - 0x80000 + 0x000F0000)

#define MVF_GPIO1_BASE_ADDR	(0x400FF000)
#define MVF_GPIO2_BASE_ADDR	(0x400FF040)
#define MVF_GPIO3_BASE_ADDR	(0x400FF080)
#define MVF_GPIO4_BASE_ADDR	(0x400FF0C0)
#define MVF_GPIO5_BASE_ADDR	(0x400FF100)

#define MVF_GPIO1_INT_BASE_ADDR	(0x40049000)
#define MVF_GPIO2_INT_BASE_ADDR	(0x4004A000)
#define MVF_GPIO3_INT_BASE_ADDR	(0x4004B000)
#define MVF_GPIO4_INT_BASE_ADDR	(0x4004C000)
#define MVF_GPIO5_INT_BASE_ADDR	(0x4004D000)

#define MVF_FEC_BASE_ADDR	MVF_MAC0_BASE_ADDR

/*
 */
#if 0

#define MVF_IO_P2V(x)			IMX_IO_P2V(x)
#define MVF_IO_ADDRESS(x)		IOMEM(MVF_IO_P2V(x))
#else
#define PERIPBASE_VIRT		0xF2000000UL
#define MVF_IO_ADDRESS(x)      (\
	(x) >= 0x40000000UL ? (void __iomem *)(x - 0x40000000 + SZ_128K	\
	+ PERIPBASE_VIRT) : (void __iomem *)(x  + PERIPBASE_VIRT)	\
	 )

#define IO_ADDRESS(x)  MVF_IO_ADDRESS(x)
#endif

/* GPC */
#define MVF_GPC_BASE		(MVF_IO_ADDRESS(MVF_GPC_BASE_ADDR))
#define MVF_PGC_IPU_BASE	(MVF_GPC_BASE + 0x220)
#define MVF_PGC_VPU_BASE	(MVF_GPC_BASE + 0x240)
#define MVF_PGC_GPU_BASE	(MVF_GPC_BASE + 0x260)
#define MVF_PGC_IPU_PGCR	(MVF_PGC_IPU_BASE + 0x0)
#define MVF_PGC_IPU_PGSR	(MVF_PGC_IPU_BASE + 0xC)
#define MVF_PGC_VPU_PGCR	(MVF_PGC_VPU_BASE + 0x0)
#define MVF_PGC_VPU_PGSR	(MVF_PGC_VPU_BASE + 0xC)
#define MVF_PGC_GPU_PGCR	(MVF_PGC_GPU_BASE + 0x0)
#define MVF_PGC_GPU_PGSR	(MVF_PGC_GPU_BASE + 0xC)

/*
 * defines for SPBA modules
 */
#define MVF_SPBA_SDHC1	0x04
#define MVF_SPBA_SDHC2	0x08
#define MVF_SPBA_UART3	0x0C
#define MVF_SPBA_CSPI1	0x10
#define MVF_SPBA_SSI2		0x14
#define MVF_SPBA_SDHC3	0x20
#define MVF_SPBA_SDHC4	0x24
#define MVF_SPBA_SPDIF	0x28
#define MVF_SPBA_ATA		0x30
#define MVF_SPBA_SLIM		0x34
#define MVF_SPBA_HSI2C	0x38
#define MVF_SPBA_CTRL		0x3C

/*
 * DMA request assignments
 */

/* DMA MUX0,3 request source number */
#define DMA_MUX03_UART0_RX	2
#define DMA_MUX03_UART0_TX	3
#define DMA_MUX03_UART1_RX	4
#define DMA_MUX03_UART1_TX	5
#define DMA_MUX03_UART2_RX	6
#define DMA_MUX03_UART2_TX	7
#define DMA_MUX03_UART3_RX	8
#define DMA_MUX03_UART3_TX	9
#define DMA_MUX03_DSPI0_RX	12
#define DMA_MUX03_DSPI0_TX	13
#define DMA_MUX03_DSPI1_RX	14
#define DMA_MUX03_DSPI1_TX	15
#define DMA_MUX03_SAI0_RX	16
#define DMA_MUX03_SAI0_TX	17
#define DMA_MUX03_SAI1_RX	18
#define DMA_MUX03_SAI1_TX	19
#define DMA_MUX03_SAI2_RX	20
#define DMA_MUX03_SAI2_TX	21
#define DMA_MUX03_PDB	22
#define DMA_MUX03_FTM0_CH0	24
#define DMA_MUX03_FTM0_CH1	25
#define DMA_MUX03_FTM0_CH2	26
#define DMA_MUX03_FTM0_CH3	27
#define DMA_MUX03_FTM0_CH4	28
#define DMA_MUX03_FTM0_CH5	29
#define DMA_MUX03_FTM0_CH6	30
#define DMA_MUX03_FTM0_CH7	31
#define DMA_MUX03_FTM1_CH0	32
#define DMA_MUX03_FTM1_CH1	33
#define DMA_MUX03_ADC0	34
#define DMA_MUX03_QUADSPI0	36
#define DMA_MUX03_GPIOA	38
#define DMA_MUX03_GPIOB	39
#define DMA_MUX03_GPIOC	40
#define DMA_MUX03_GPIOD	41
#define DMA_MUX03_GPIOE	42
#define DMA_MUX03_RLE_RX	45
#define DMA_MUX03_RLE_TX	46
#define DMA_MUX03_SPDIF_RX	47
#define DMA_MUX03_SPDIF_TX	48
#define DMA_MUX03_I2C0_RX	50
#define DMA_MUX03_I2C0_TX	51
#define DMA_MUX03_I2C1_RX	52
#define DMA_MUX03_I2C1_TX	53
#define DMA_MUX03_ALWAYS0	54
#define DMA_MUX03_ALWAYS1	55
#define DMA_MUX03_ALWAYS2	56
#define DMA_MUX03_ALWAYS3	57
#define DMA_MUX03_ALWAYS4	58
#define DMA_MUX03_ALWAYS5	59
#define DMA_MUX03_ALWAYS6	60
#define DMA_MUX03_ALWAYS7	61
#define DMA_MUX03_ALWAYS8	62
#define DMA_MUX03_ALWAYS9	63

/* DMA MUX1,2 request source number */
#define DMA_MUX12_UART4_RX	2
#define DMA_MUX12_UART4_TX	3
#define DMA_MUX12_UART5_RX	4
#define DMA_MUX12_UART5_TX	5
#define DMA_MUX12_SAI3_RX	8
#define DMA_MUX12_SAI3_TX	9
#define DMA_MUX12_DSPI2_RX	10
#define DMA_MUX12_DSPI2_TX	11
#define DMA_MUX12_DSPI3_RX	12
#define DMA_MUX12_DSPI3_TX	13
#define DMA_MUX12_FTM2_CH0	16
#define DMA_MUX12_FTM2_CH1	17
#define DMA_MUX12_FTM3_CH0	18
#define DMA_MUX12_FTM3_CH1	19
#define DMA_MUX12_FTM3_CH2	20
#define DMA_MUX12_FTM3_CH3	21
#define DMA_MUX12_FTM3_CH4	22
#define DMA_MUX12_FTM3_CH5	24
#define DMA_MUX12_FTM3_CH6	25
#define DMA_MUX12_FTM3_CH7	26
#define DMA_MUX12_QUADSPI1	27
#define DMA_MUX12_DAC0	32
#define DMA_MUX12_DAC1	33
#define DMA_MUX12_ESAI_BIFIFO_TX	34
#define DMA_MUX12_ESAI_BIFIFO_RX	35
#define DMA_MUX12_I2C2_RX	36
#define DMA_MUX12_I2C2_TX	37
#define DMA_MUX12_I2C3_RX	38
#define DMA_MUX12_I2C3_TX	39
#define DMA_MUX12_ASRC0_TX	40
#define DMA_MUX12_ASRC0_RX	41
#define DMA_MUX12_ASRC1_TX	42
#define DMA_MUX12_ASRC1_RX	43
#define DMA_MUX12_TIMER0	44
#define DMA_MUX12_TIMER1	45
#define DMA_MUX12_TIMER2	46
#define DMA_MUX12_TIMER3	47
#define DMA_MUX12_TIMER4	48
#define DMA_MUX12_TIMER5	49
#define DMA_MUX12_TIMER6	50
#define DMA_MUX12_TIMER7	51
#define DMA_MUX12_ASRC2_TX	52
#define DMA_MUX12_ASRC2_RX	53
#define DMA_MUX12_ALWAYS0	54
#define DMA_MUX12_ALWAYS1	55
#define DMA_MUX12_ALWAYS2	56
#define DMA_MUX12_ALWAYS3	57
#define DMA_MUX12_ALWAYS4	58
#define DMA_MUX12_ALWAYS5	59
#define DMA_MUX12_ALWAYS6	60
#define DMA_MUX12_ALWAYS7	61
#define DMA_MUX12_ALWAYS8	62
#define DMA_MUX12_ALWAYS9	63


/* 16 DMA channel per MUX*/
#define DMAMUX0_CHCFG0		MVF_DMAMUX0_BASE_ADDR
#define DMAMUX0_CHCFG(n)	(MVF_DMAMUX0_BASE_ADDR + 8*(n))
#define DMAMUX1_CHCFG0		MVF_DMAMUX1_BASE_ADDR
#define DMAMUX1_CHCFG(n)	(MVF_DMAMUX1_BASE_ADDR + 8*(n))
#define DMAMUX2_CHCFG0		MVF_DMAMUX2_BASE_ADDR
#define DMAMUX2_CHCFG(n)	(MVF_DMAMUX2_BASE_ADDR + 8*(n))
#define DMAMUX3_CHCFG0		MVF_DMAMUX3_BASE_ADDR
#define DMAMUX3_CHCFG(n)	(MVF_DMAMUX3_BASE_ADDR + 8*(n))


/* DMA slot number 53 periph and 10 alway-on source */
#define MVF_DMA_REQ_SSI3_TX0		47
#define MVF_DMA_REQ_SSI3_RX0		46
#define MVF_DMA_REQ_SSI3_TX1		45
#define MVF_DMA_REQ_SSI3_RX1		44
#define MVF_DMA_REQ_UART3_TX	43
#define MVF_DMA_REQ_UART3_RX	42
#define MVF_DMA_REQ_ESAI_TX		41
#define MVF_DMA_REQ_ESAI_RX		40
#define MVF_DMA_REQ_CSPI_TX		39
#define MVF_DMA_REQ_CSPI_RX		38
#define MVF_DMA_REQ_ASRC_DMA6	37
#define MVF_DMA_REQ_ASRC_DMA5	36
#define MVF_DMA_REQ_ASRC_DMA4	35
#define MVF_DMA_REQ_ASRC_DMA3	34
#define MVF_DMA_REQ_ASRC_DMA2	33
#define MVF_DMA_REQ_ASRC_DMA1	32
#define MVF_DMA_REQ_EMI_WR		31
#define MVF_DMA_REQ_EMI_RD		30
#define MVF_DMA_REQ_SSI1_TX0		29
#define MVF_DMA_REQ_SSI1_RX0		28
#define MVF_DMA_REQ_SSI1_TX1		27
#define MVF_DMA_REQ_SSI1_RX1		26
#define MVF_DMA_REQ_SSI2_TX0		25
#define MVF_DMA_REQ_SSI2_RX0		24
#define MVF_DMA_REQ_SSI2_TX1		23
#define MVF_DMA_REQ_SSI2_RX1		22
#define MVF_DMA_REQ_I2C2_SDHC2	21
#define MVF_DMA_REQ_I2C1_SDHC1	20
#define MVF_DMA_REQ_UART1_TX	19
#define MVF_DMA_REQ_UART1_RX	18
#define MVF_DMA_REQ_UART5_TX	17
#define MVF_DMA_REQ_UART5_RX	16
#define MVF_DMA_REQ_SPDIF_TX		15
#define MVF_DMA_REQ_SPDIF_RX		14
#define MVF_DMA_REQ_UART2_FIRI_TX	13
#define MVF_DMA_REQ_UART2_FIRI_RX	12
#define MVF_DMA_REQ_SDHC4		11
#define MVF_DMA_REQ_I2C3_SDHC3	10
#define MVF_DMA_REQ_CSPI2_TX		9
#define MVF_DMA_REQ_CSPI2_RX		8
#define MVF_DMA_REQ_CSPI1_TX		7
#define MVF_DMA_REQ_CSPI1_RX		6
#define MVF_DMA_REQ_IPU		5
#define MVF_DMA_REQ_ATA_TX_END	4
#define MVF_DMA_REQ_ATA_UART4_TX	3
#define MVF_DMA_REQ_ATA_UART4_RX	2
#define MVF_DMA_REQ_GPC		1
#define MVF_DMA_REQ_VPU		0

/*
 * Interrupt Vector numbers
 */
#define MXC_INT_START		27
#define MVF_INT_GLOBAL_TIMER	27
#define MVF_INT_LEGACY_NFIQ	28
#define MVF_INT_CORE_TIMER	29
#define MVF_INT_CORE_WDOG1	30
#define MVF_INT_LEGACY_NIRQ	31
#define MVF_INT_CPU_INT0	32
#define MVF_INT_CPU_INT1	33
#define MVF_INT_CPU_INT2	34
#define MVF_INT_CPU_INT3	35
#define MVF_INT_SEMA4		36
#define MVF_INT_DBG		37
#define MVF_INT_L2CC		38
#define MVF_INT_PMU		39
#define MVF_INT_DMA0_TX		40
#define MVF_INT_DMA0_ERR	41
#define MVF_INT_DMA1_TX		42
#define MVF_INT_DMA1_ERR	43
#define MVF_INT_MSCM_ECC0	46
#define MVF_INT_MSCM_ECC1	47
#define MVF_INT_CSU_ALARM	48
#define MVF_INT_MSCM_ACTZS	50
#define MVF_INT_WDOG		52
#define MVF_INT_WDOG_SNVS	54
#define MVF_INT_QUADSPI0	56
#define MVF_INT_QUADSPI1	57
#define MVF_INT_DDRMC		58
#define MVF_INT_ESDHC0		59
#define MVF_INT_ESDHC1		60
#define MVF_INT_DCU0		62
#define MVF_INT_DCU1		63
#define MVF_INT_VIU		64
#define MVF_INT_GC355		66
#define MVF_INT_RLE		67
#define MVF_INT_SEG_LCD		68
#define MVF_INT_PIT		71
#define MVF_INT_LPTIMER0	72
#define MVF_INT_FLEXTIMER0	74
#define MVF_INT_FLEXTIMER1	75
#define MVF_INT_FLEXTIMER2	76
#define MVF_INT_FLEXTIMER3	77
#define MVF_INT_ANATOP_USBPHY0	82
#define MVF_INT_ANATOP_USBPHY1	83
#define MVF_INT_ADC0		85
#define MVF_INT_ADC1		86
#define MVF_INT_DAC0		87
#define MVF_INT_DAC1		88
#define MVF_INT_CAN0		90
#define MVF_INT_CAN1		91
#define MVF_INT_MLB		92
#define MVF_INT_UART0		93
#define MVF_INT_UART1		94
#define MVF_INT_UART2		95
#define MVF_INT_UART3		96
#define MVF_INT_UART4		97
#define MVF_INT_UART5		98
#define MVF_INT_DSPI0		99
#define MVF_INT_DSPI1		100
#define MVF_INT_DSPI2		101
#define MVF_INT_DSPI3		102
#define MVF_INT_I2C0		103
#define MVF_INT_I2C1		104
#define MVF_INT_I2C2		105
#define MVF_INT_I2C3		106
#define MVF_INT_USBOTG0		107
#define MVF_INT_USB2		108
#define MVF_INT_ENET_MAC0	110
#define MVF_INT_ENET_MAC1	111
#define MVF_INT_1588_TIMER0	112
#define MVF_INT_1588_TIMER1	113
#define MVF_INT_ENET_SWITCH	114
#define MVF_INT_NFC		115
#define MVF_INT_SAI0		116
#define MVF_INT_SAI1		117
#define MVF_INT_SAI2		118
#define MVF_INT_SAI3		119
#define MVF_INT_ESAI_BIFIFO	120
#define MVF_INT_SPDIF		121
#define MVF_INT_ASRC		122
#define MVF_INT_CMU		123
#define MVF_INT_WKPU0		124
#define MVF_INT_WKPU1		125
#define MVF_INT_CCM		126

#define MVF_INT_SRC		128
#define MVF_INT_PDB		129
#define MVF_INT_EWM		130
#define MVF_INT_SNVS		132

#define MVF_INT_CAAM		134

#define MVF_INT_GPIO0		139
#define MVF_INT_GPIO1		140
#define MVF_INT_GPIO2		141
#define MVF_INT_GPIO3		142
#define MVF_INT_GPIO4		143
#define MXC_INT_END		143

#define MVF_INT_FEC	MVF_INT_ENET_MAC0

/* silicon revisions specific to i.MVF */
#define MVF_CHIP_REV_1_0		0x10
#define MVF_CHIP_REV_1_1		0x11
#define MVF_CHIP_REV_1_2		0x12
#define MVF_CHIP_REV_1_3		0x13
#define MVF_CHIP_REV_2_0		0x20
#define MVF_CHIP_REV_2_1		0x21
#define MVF_CHIP_REV_2_2		0x22
#define MVF_CHIP_REV_2_3		0x23
#define MVF_CHIP_REV_3_0		0x30
#define MVF_CHIP_REV_3_1		0x31
#define MVF_CHIP_REV_3_2		0x32

/*!
 * IIM bank info
 */
#define MXC_IIM_MX51_BANK_START_ADDR 0x0800
#define MXC_IIM_MX51_BANK_END_ADDR   0x147c
#define MXC_IIM_MVF_BANK_START_ADDR 0x0800
#define MXC_IIM_MVF_BANK_END_ADDR   0x183c
#define MXC_IIM_MVF_BANK_AREA_1_OFFSET 0xc00
#define MXC_IIM_MVF_MAC_ADDR_OFFSET    0x24

#endif /* ifndef __MACH_MVF_H__ */