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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/dts-v1/;
#include "fsl-imx8mm-evk.dts"
/ {
model = "FSL i.MX8MM DDR4 EVK board";
busfreq {
status = "disabled";
};
};
&iomuxc {
imx8mm-evk {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
};
&usdhc3 {
status = "disabled";
};
&flexspi {
status = "disabled";
};
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