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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Freescale LS2088A QDS Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
*
*/
/dts-v1/;
#include "fsl-ls2088a.dtsi"
#include "fsl-ls208xa-qds.dtsi"
/ {
model = "Freescale Layerscape 2088A QDS Board";
compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
chosen {
stdout-path = "serial0:115200n8";
};
};
&ifc {
boardctrl: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
reg = <3 0 0x300>; /* TODO check address */
ranges = <0 3 0 0x300>;
mdio_mux_emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&emdio1>;
reg = <0x54 1>; /* BRDCFG4 */
mux-mask = <0xe0>; /* EMI1_MDIO */
#address-cells=<1>;
#size-cells = <0>;
/* Child MDIO buses, one for each riser card:
* reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
* VSC8234 PHYs on the riser cards.
*/
mdio_mux3: mdio@60 {
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
mdio0_phy12: mdio_phy0@1c {
reg = <0x1c>;
phy-connection-type = "sgmii";
};
mdio0_phy13: mdio_phy1@1d {
reg = <0x1d>;
phy-connection-type = "sgmii";
};
mdio0_phy14: mdio_phy2@1e {
reg = <0x1e>;
phy-connection-type = "sgmii";
};
mdio0_phy15: mdio_phy3@1f {
reg = <0x1f>;
phy-connection-type = "sgmii";
};
};
};
};
};
&pcs_mdio1 {
pcs_phy1: ethernet-phy@0 {
backplane-mode = "10gbase-kr";
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
fsl,lane-handle = <&serdes1>;
fsl,lane-reg = <0x9C0 0x40>;/* lane H */
};
};
&pcs_mdio2 {
pcs_phy2: ethernet-phy@0 {
backplane-mode = "10gbase-kr";
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
fsl,lane-handle = <&serdes1>;
fsl,lane-reg = <0x980 0x40>;/* lane G */
};
};
&pcs_mdio3 {
pcs_phy3: ethernet-phy@0 {
backplane-mode = "10gbase-kr";
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
fsl,lane-handle = <&serdes1>;
fsl,lane-reg = <0x940 0x40>;/* lane F */
};
};
&pcs_mdio4 {
pcs_phy4: ethernet-phy@0 {
backplane-mode = "10gbase-kr";
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
fsl,lane-handle = <&serdes1>;
fsl,lane-reg = <0x900 0x40>;/* lane E */
};
};
/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
* &dpmac1 {
* phy-handle = <&pcs_phy1>;
* };
*
* &dpmac2 {
* phy-handle = <&pcs_phy2>;
* };
*
* &dpmac3 {
* phy-handle = <&pcs_phy3>;
* };
*
* &dpmac4 {
* phy-handle = <&pcs_phy4>;
* };
*/
/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
phy-handle = <&mdio0_phy12>;
};
&dpmac10 {
phy-handle = <&mdio0_phy13>;
};
&dpmac11 {
phy-handle = <&mdio0_phy14>;
};
&dpmac12 {
phy-handle = <&mdio0_phy15>;
};
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