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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Richard Zhu <hongxing.zhu@nxp.com>
*/
#include <dt-bindings/soc/imx8_hsio.h>
hsio_subsys: bus@5f000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
/* Only supports up to 32bits DMA, map all possible DDR as inbound ranges */
dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
ranges = <0x5f000000 0x0 0x5f000000 0x21000000>;
xtal100m: clock-xtal100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "xtal_100MHz";
};
hsio_refa_clk: clock-hsio-refa {
compatible = "gpio-gate-clock";
clocks = <&xtal100m>;
#clock-cells = <0>;
enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
};
hsio_refb_clk: clock-hsio-refb {
compatible = "gpio-gate-clock";
clocks = <&xtal100m>;
#clock-cells = <0>;
enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
};
hsio_axi_clk: clock-hsio-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
clock-output-names = "hsio_axi_clk";
};
hsio_per_clk: clock-hsio-per {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133333333>;
clock-output-names = "hsio_per_clk";
};
pcieb_lpcg: clock-controller@5f060000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f060000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
bit-offset = <16 20 24>;
clock-output-names = "hsio_pcieb_mstr_axi_clk",
"hsio_pcieb_slv_axi_clk",
"hsio_pcieb_dbi_axi_clk";
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
phyx1_crr1_lpcg: clock-controller@5f0b0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0b0000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_per_clk>;
bit-offset = <16>;
clock-output-names = "hsio_phyx1_per_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
pcieb_crr3_lpcg: clock-controller@5f0d0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0d0000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_per_clk>;
bit-offset = <16>;
clock-output-names = "hsio_pcieb_per_clk";
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
misc_crr5_lpcg: clock-controller@5f0f0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0f0000 0x10000>;
#clock-cells = <1>;
clocks = <&hsio_per_clk>;
bit-offset = <16>;
clock-output-names = "hsio_misc_per_clk";
power-domains = <&pd IMX_SC_R_HSIO_GPIO>;
};
pcieb: pcie@0x5f010000 {
compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
reg = <0x5f010000 0x10000>, /* Controller reg */
<0x7ff00000 0x80000>, /* PCI cfg space */
<0x5f110000 0x60000>; /* lpcg, csr, msic, gpio */
reg-names = "dbi", "config", "hsio";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x7ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x70000000 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "msi", "dma";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
/*
* Set the clks/pds for imx8qxp in default, clks/pds should be
* refined for exact hw design of imx8 pcie.
For example, when hsio-cfg = <PCIEAX1PCIEBX1SATA>,
set clks below.
clocks = <&hsio_lpcg IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
<&hsio_lpcg IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
<&hsio_lpcg IMX8QM_HSIO_PHY_X2_PCLK_1>,
<&hsio_lpcg IMX8QM_HSIO_PCIE_X1_PER_CLK>,
<&hsio_lpcg IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
*/
clocks = <&pcieb_lpcg 0>,
<&pcieb_lpcg 1>,
<&pcieb_lpcg 2>,
<&phyx1_lpcg 0>,
<&phyx1_crr1_lpcg 0>,
<&pcieb_crr3_lpcg 0>,
<&misc_crr5_lpcg 0>;
clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
"pcie_phy", "phy_per","pcie_per", "misc_per";
power-domains = <&pd IMX_SC_R_PCIE_B>,
<&pd IMX_SC_R_SERDES_1>,
<&pd IMX_SC_R_HSIO_GPIO>;
power-domain-names = "pcie", "pcie_phy", "hsio_gpio";
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX2PCIEBX1>;
local-addr = <0x80000000>;
status = "disabled";
};
};
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