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|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019~2020 NXP
*/
/dts-v1/;
#include "imx8dxl.dtsi"
/ {
model = "Freescale i.MX8DXL MEK";
compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";
chosen {
stdout-path = &lpuart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/*
* 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
* Shouldn't be used at A core and Linux side.
*
*/
m4_reserved: m4@0x88000000 {
no-map;
reg = <0 0x88000000 0 0x8000000>;
};
rpmsg_reserved: rpmsg@0x90000000 {
no-map;
reg = <0 0x90000000 0 0x400000>;
};
rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
compatible = "shared-dma-pool";
no-map;
reg = <0 0x90400000 0 0x100000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
alloc-ranges = <0 0x96000000 0 0x3c000000>;
linux,cma-default;
};
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <3480>;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&lsio_gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
mt35xu512aba0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
pca9548@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pca6416_1: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
pca6416_2: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lsio_gpio4 {
status = "okay";
};
&lsio_gpio5 {
status = "okay";
};
&pcieb{
compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "disabled";
};
&thermal_zones {
pmic-thermal0 {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&tsens 497>;
trips {
pmic_alert0: trip0 {
temperature = <110000>;
hysteresis = <2000>;
type = "passive";
};
pmic_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&pmic_alert0>;
cooling-device =
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
vmmc-supply = <®_usdhc2_vmmc>;
cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <ðphy0>;
snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <10 20 200000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
};
};
};
&usbphy1 {
status = "okay";
};
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
power-polarity-active-high;
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8DXL_UART0_RX_ADMA_UART0_RX 0x0600004c
IMX8DXL_UART0_TX_ADMA_UART0_TX 0x0600004c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_pcieb: pcieagrp{
fsl,pins = <
IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
>;
};
};
|
