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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019~2020 NXP
*/
/delete-node/ &enet1_lpcg;
/delete-node/ &fec2;
&usdhc1 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
};
&usdhc2 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
};
&usdhc3 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
&enet0_lpcg {
clocks = <&conn_enet0_root_clk>,
<&conn_enet0_root_clk>,
<&conn_axi_clk>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
<&conn_ipg_clk>,
<&conn_ipg_clk>;
};
&fec1 {
compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec";
};
&conn_subsys {
conn_enet0_root_clk: clock-conn-enet0-root {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
clock-output-names = "conn_enet0_root_clk";
};
eqos_lpcg: clock-controller@5b240000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b240000 0x10000>;
#clock-cells = <1>;
clocks = <&conn_enet0_root_clk>,
<&conn_axi_clk>,
<&conn_axi_clk>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>;
bit-offset = <0 8 16 20 24>;
clock-output-names = "eqos_ptp",
"eqos_mem_clk",
"eqos_aclk",
"eqos_clk",
"eqos_csr_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
eqos: ethernet@5b050000 {
compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x5b050000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eth_wake_irq", "macirq";
clocks = <&eqos_lpcg 2>,
<&eqos_lpcg 4>,
<&eqos_lpcg 0>,
<&eqos_lpcg 3>,
<&eqos_lpcg 1>;
clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <125000000>;
power-domains = <&pd IMX_SC_R_ENET_1>;
clk_csr = <0>;
status = "disabled";
};
};
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