blob: 4fad48aa514a351601b697926b3deda10b3e19dd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mq-evk.dts"
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
m4_reserved: m4@0x80000000 {
no-map;
reg = <0 0x80000000 0 0x1000000>;
};
rpmsg_reserved: rpmsg@0xb8000000 {
no-map;
reg = <0 0xb8200000 0 0x200000>;
};
vdev0vring0: vdev0vring0@b8000000 {
compatible = "shared-dma-pool";
reg = <0 0xb8000000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@b8008000 {
compatible = "shared-dma-pool";
reg = <0 0xb8008000 0 0x8000>;
no-map;
};
vdevbuffer: vdevbuffer@b8400000 {
compatible = "shared-dma-pool";
reg = <0 0xb8400000 0 0x100000>;
no-map;
};
};
imx8mq-cm4 {
compatible = "fsl,imx8mq-cm4";
rsc-da = <0xb8000000>;
clocks = <&clk IMX8MQ_CLK_M4_DIV>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&mu 0 1
&mu 1 1
&mu 3 1>;
memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>;
syscon = <&src>;
};
};
/*
* Regarding to the HW conflications, the following module should be disabled
* when M4 is running on evk board.
* gpt1, i2c2, pwm4, tmu, uart2
*/
&i2c2 {
status = "disabled";
};
&pwm4 {
status = "disabled";
};
&rpmsg{
/*
* 64K for one rpmsg instance:
* --0xb8000000~0xb800ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8000000 0x0 0x10000>;
memory-region = <&vdevbuffer>;
status = "disabled";
};
&tmu {
status = "disabled";
};
&uart2 {
status = "disabled";
};
|