path: root/arch/arm64/boot/dts/freescale/imx8qm-mek.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	cpus {
		/delete-node/ cpu-map;
		/delete-node/ cpu@100;
		/delete-node/ cpu@101;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pinctrl_modem_reset>;
		pinctrl-1 = <&pinctrl_modem_reset_sleep>;
		reset-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};
		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x400000>;
		};
		/*
		 * reserved-memory layout
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};
		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};
		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x90400000 0 0x100000>;
		};
		decoder_rpc: decoder_rpc@0x92000000 {
			no-map;
			reg = <0 0x92000000 0 0x200000>;
		};
		encoder_rpc: encoder_rpc@0x92200000 {
			no-map;
			reg = <0 0x92200000 0 0x200000>;
		};
		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};
		encoder_reserved: encoder_reserved@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
			linux,cma-default;
		};

	};

	reg_fec2_supply: fec2_nvcc {
		compatible = "regulator-fixed";
		regulator-name = "fec2_nvcc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_en: regulator-can01-gen {
		compatible = "regulator-fixed";
		regulator-name = "can01-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_en: regulator-can2-gen {
		compatible = "regulator-fixed";
		regulator-name = "can2-en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can01_stby: regulator-can01-stby {
		compatible = "regulator-fixed";
		regulator-name = "can01-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can01_en>;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		regulator-name = "can2-stby";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&reg_can2_en>;
	};
};

&cm41_i2c {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_cm41_i2c>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&cm41_intmux {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&i2c1_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;

		port {
			it6263_0_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
};

&ldb1_phy {
	status = "okay";
};

&ldb1 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds0_out: endpoint {
				remote-endpoint = <&it6263_0_in>;
			};
		};
	};
};

&dpu2 {
	status = "okay";
};

&i2c1_lvds1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;

		port {
			it6263_1_in: endpoint {
				remote-endpoint = <&lvds1_out>;
			};
		};
	};
};

&ldb2_phy {
	status = "okay";
};

&ldb2 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds1_out: endpoint {
				remote-endpoint = <&it6263_1_in>;
			};
		};
	};
};

&lpspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
	cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <30000000>;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	resets = <&modem_reset>;
	status = "okay";
};

&lpuart2 { /* Dbg console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "disabled";
};

&lpuart3 { /* MKbus */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "disabled";
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can01_stby>;
	status = "okay";
};

&flexcan3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan3>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac0>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_fec2_supply>;
	fsl,magic-packet;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	fsl,rgmii_rxc_dly;
	status = "okay";
};

&pciea{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pciea>;
	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
	clkreq-gpio = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	status = "okay";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90000000 0x0 0x20000>;
	memory-region = <&rpmsg_dma_reserved>;
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	max7322: gpio@68 {
		compatible = "maxim,max7322";
		reg = <0x68>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&isi_0 {
	status = "okay";
};

&isi_4 {
	status = "okay";
};

&irqsteer_csi0 {
	status = "okay";
};

&irqsteer_csi1 {
	status = "okay";
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	/* Camera 0  MIPI CSI-2 (CSIS0) */
	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&ov5640_mipi_0_ep>;
			data-lanes = <1 2>;
			bus-type = <4>;
		};
	};
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	/* Camera 0  MIPI CSI-2 (CSIS0) */
	port@1 {
		reg = <1>;
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&ov5640_mipi_1_ep>;
			data-lanes = <1 2>;
			bus-type = <4>;
		};
	};
};

&i2c_mipi_csi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi0>;
	clock-frequency = <100000>;
	status = "okay";

	ov5640_mipi_0: ov5640_mipi@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi0>;
		clocks = <&xtal24m>;
		clock-names = "xclk";
		csi_id = <0>;
		powerdown-gpios = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&lsio_gpio1 27 GPIO_ACTIVE_LOW>;
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;
		status = "okay";
		port {
			ov5640_mipi_0_ep: endpoint {
				remote-endpoint = <&mipi_csi0_ep>;
				data-lanes = <1 2>;
				clocks-lanes = <0>;
			};
		};
	};
};

&i2c_mipi_csi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c_mipi_csi1>;
	clock-frequency = <100000>;
	status = "okay";

	ov5640_mipi_1: ov5640_mipi@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_csi1>;
		clocks = <&xtal24m>;
		clock-names = "xclk";
		csi_id = <0>;
		powerdown-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_LOW>;
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;
		status = "okay";
		port {
			ov5640_mipi_1_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
				data-lanes = <1 2>;
				clocks-lanes = <0>;
			};
		};
	};
};

&iomuxc {
	pinctrl_cm41_i2c: cm41i2cgrp {
		fsl,pins = <
			IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA			0x0600004c
			IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL			0x0600004c
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD		0x000014a0
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_fec2: fec2grp {
		fsl,pins = <
			IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD		0x000014a0
			IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC		0x00000060
			IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0		0x00000060
			IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1		0x00000060
			IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2		0x00000060
			IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3		0x00000060
			IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC		0x00000060
			IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
			IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0		0x00000060
			IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1		0x00000060
			IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2		0x00000060
			IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3		0x00000060
		>;
	};

	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX            0x21
			IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX            0x21
		>;
	};

	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX            0x21
			IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX            0x21
			>;
	};

	pinctrl_flexcan3: flexcan3grp {
		fsl,pins = <
			IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX            0x21
			IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX            0x21
			>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
			IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
			IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
		>;
	};

	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <
			IMX8QM_SPI2_SCK_DMA_SPI2_SCK		0x0600004c
			IMX8QM_SPI2_SDO_DMA_SPI2_SDO		0x0600004c
			IMX8QM_SPI2_SDI_DMA_SPI2_SDI		0x0600004c
			IMX8QM_SPI2_CS0_DMA_SPI2_CS0		0x0600004c
		>;
	};

	pinctrl_lpspi2_cs: lpspi2cs {
		fsl,pins = <
			IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10		0x21
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_lpuart1: lpuart1grp {
		fsl,pins = <
			IMX8QM_UART1_RX_DMA_UART1_RX		0x06000020
			IMX8QM_UART1_TX_DMA_UART1_TX		0x06000020
			IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
			IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QM_UART0_RTS_B_DMA_UART2_RX		0x06000020
			IMX8QM_UART0_CTS_B_DMA_UART2_TX		0x06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QM_M41_GPIO0_00_DMA_UART3_RX		0x06000020
			IMX8QM_M41_GPIO0_01_DMA_UART3_TX		0x06000020
		>;
	};

	pinctrl_modem_reset: modemresetgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22		0x06000021
		>;
	};

	pinctrl_modem_reset_sleep: modemreset_sleepgrp {
		fsl,pins = <
			IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22		0x07800021
		>;
	};

	pinctrl_pciea: pcieagrp{
		fsl,pins = <
			IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27		0x06000021
			IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
			IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
		>;
	};

	pinctrl_usbotg1: usbotg1 {
		fsl,pins = <
			IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
		fsl,pins = <
			IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21			0x00000021
			IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22			0x00000021
			IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07			0x00000021
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};

	pinctrl_i2c_mipi_csi0: i2c_mipi_csi0 {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_i2c_mipi_csi1: i2c_mipi_csi1 {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL		0xc2000020
			IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA		0xc2000020
		>;
	};

	pinctrl_mipi_csi0: mipi_csi0 {
		fsl,pins = <
			IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27		0xC0000041
			IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0xC0000041
			IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_mipi_csi1: mipi_csi1 {
		fsl,pins = <
			IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30		0xC0000041
			IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31		0xC0000041
			IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT	0xC0000041
		>;
	};

	pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
			IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
		>;
	};

	pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
		fsl,pins = <
			IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
			IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
		>;
	};
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};
			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};
		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};