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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
&dpu1 {
compatible = "fsl,imx8qm-dpu";
clocks = <&clk IMX_SC_R_DC_0_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_0 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "disp0", "disp1";
dpu1_disp0: port@0 {
reg = <0>;
};
dpu1_disp1: port@1 {
reg = <1>;
dpu1_disp1_ldb1_ch0: endpoint@0 {
remote-endpoint = <&ldb1_ch0>;
};
dpu1_disp1_ldb1_ch1: endpoint@1 {
remote-endpoint = <&ldb1_ch1>;
};
};
};
&dpu2 {
compatible = "fsl,imx8qm-dpu";
clocks = <&clk IMX_SC_R_DC_1_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC0>,
<&clk IMX_SC_R_DC_1 IMX_SC_PM_CLK_MISC1>;
clock-names = "pll0", "pll1", "disp0", "disp1";
power-domains = <&pd IMX_SC_R_DC_1>,
<&pd IMX_SC_R_DC_1_PLL_0>,
<&pd IMX_SC_R_DC_1_PLL_1>;
power-domain-names = "dc", "pll0", "pll1";
status = "disabled";
dpu2_disp0: port@0 {
reg = <0>;
};
dpu2_disp1: port@1 {
reg = <1>;
dpu2_disp1_ldb2_ch0: endpoint@0 {
remote-endpoint = <&ldb2_ch0>;
};
dpu2_disp1_ldb2_ch1: endpoint@1 {
remote-endpoint = <&ldb2_ch1>;
};
};
};
/ {
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&dpu1_disp0>, <&dpu1_disp1>,
<&dpu2_disp0>, <&dpu2_disp1>;
};
};
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