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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
/ {
panel {
compatible = "sii,43wvf1g";
backlight = <&lcdif_backlight>;
status = "okay";
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcd_display_out>;
};
};
};
display@disp1 {
compatible = "fsl,imx-lcdif-mux-display";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
<&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
clock-names = "bypass_div", "pixel";
assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
fsl,interface-pix-fmt = "rgb666";
power-domains = <&pd IMX_SC_R_LCD_0>;
status = "okay";
port@0 {
reg = <0>;
lcd_display_in: endpoint {
remote-endpoint = <&dpu_disp1_lcdif>;
};
};
port@1 {
reg = <1>;
lcd_display_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
};
&dpu_disp1_lcdif {
remote-endpoint = <&lcd_display_in>;
};
&iomuxc {
pinctrl_hog: hoggrp {
fsl,pins = <
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x40000000
>;
};
};
&sai1 {
status = "disabled";
};
&esai0 {
status = "disabled";
};
&lpuart1 {
status = "disabled";
};
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