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/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 MicroSys Electronics GmbH
* Copyright 2018-2019 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "s32v234.dtsi"
/ {
model = "Freescale S32V234";
compatible = "fsl,s32v234-sbc", "fsl,s32v234";
chosen {
stdout-path = "serial0:115200n8";
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&siul2 {
status = "okay";
s32v234-sbc {
/* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the
* IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference
* Manual states.
*/
pinctrl_enet: enetgrp {
fsl,pins = <
S32V234_PAD_PC13__MDC
S32V234_PAD_PC14__MDIO_OUT
S32v234_PAD_PC14__MDIO_IN
S32V234_PAD_PC15__TXCLK_OUT
S32V234_PAD_PC15__TXCLK_IN
S32V234_PAD_PD0__RXCLK_OUT
S32V234_PAD_PD0__RXCLK_IN
S32V234_PAD_PD1__RX_D0_OUT
S32V234_PAD_PD1__RX_D0_IN
S32V234_PAD_PD2__RX_D1_OUT
S32V234_PAD_PD2__RX_D1_IN
S32V234_PAD_PD3__RX_D2_OUT
S32V234_PAD_PD3__RX_D2_IN
S32V234_PAD_PD4__RX_D3_OUT
S32V234_PAD_PD4__RX_D3_IN
S32V234_PAD_PD4__RX_DV_OUT
S32V234_PAD_PD4__RX_DV_IN
S32V234_PAD_PD7__TX_D0_OUT
S32V234_PAD_PD8__TX_D1_OUT
S32V234_PAD_PD9__TX_D2_OUT
S32V234_PAD_PD10__TX_D3_OUT
S32V234_PAD_PD11__TX_EN_OUT
>;
};
pinctrl_uart0: uart0grp {
fsl,pins = <
12 PAD_CTL_UART_TX
11 PAD_CTL_UART_RX_MSCR
712 PAD_CTL_UART_RX_IMCR
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
14 PAD_CTL_UART_TX
13 PAD_CTL_UART_RX_MSCR
714 PAD_CTL_UART_RX_IMCR
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
150 PAD_CTL_USDHC_CLK
902 PAD_CTL_MUX_MODE_ALT3
151 PAD_CTL_USDHC_CMD
901 PAD_CTL_MUX_MODE_ALT3
152 PAD_CTL_USDHC_DAT0_3
903 PAD_CTL_MUX_MODE_ALT3
153 PAD_CTL_USDHC_DAT0_3
904 PAD_CTL_MUX_MODE_ALT3
154 PAD_CTL_USDHC_DAT0_3
905 PAD_CTL_MUX_MODE_ALT3
155 PAD_CTL_USDHC_DAT0_3
906 PAD_CTL_MUX_MODE_ALT3
159 PAD_CTL_USDHC_DAT4_7
907 PAD_CTL_MUX_MODE_ALT3
160 PAD_CTL_USDHC_DAT4_7
908 PAD_CTL_MUX_MODE_ALT3
161 PAD_CTL_USDHC_DAT4_7
909 PAD_CTL_MUX_MODE_ALT3
162 PAD_CTL_USDHC_DAT4_7
910 PAD_CTL_MUX_MODE_ALT3
>;
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc0 {
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
status = "okay";
};
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