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|
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J722S SoC Family
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>
#include "k3-am62p5.dtsi"
/*
* USB1 controller on AM62P and J722S are of different IP.
* Delete AM62P's USBSS1 node definition and redefine it for J722S.
*/
/delete-node/ &usbss1;
/ {
model = "Texas Instruments K3 J722S SoC";
compatible = "ti,j722s";
cbass_main: bus@f0000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
<0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
<0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
<0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
<0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
<0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
<0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
<0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
<0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
<0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
<0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
<0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
<0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
<0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
<0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>,
<0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>,
<0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>,
<0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>,
/* Wakeup Domain Range */
<0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>,
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>,
<0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>,
<0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>;
};
serdes_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
usbss1: cdns-usb@f920000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x0f920000 0x00 0x100>;
power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb1: usb@31200000{
compatible = "cdns,usb3";
reg = <0x00 0x31200000 0x00 0x10000>,
<0x00 0x31210000 0x00 0x10000>,
<0x00 0x31220000 0x00 0x10000>;
reg-names = "otg",
"xhci",
"dev";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
serdes_wiz0: wiz@f000000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <1>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
assigned-clocks = <&k3_clks 279 1>;
assigned-clock-parents = <&k3_clks 279 5>;
serdes0: serdes@f000000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x0f000000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 279 1>,
<&k3_clks 279 1>,
<&k3_clks 279 1>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
status = "disabled"; /* Needs lane config */
};
};
serdes_wiz1: wiz@f010000 {
compatible = "ti,am64-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
num-lanes = <1>;
#reset-cells = <1>;
#clock-cells = <1>;
ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
assigned-clocks = <&k3_clks 280 1>;
assigned-clock-parents = <&k3_clks 280 5>;
serdes1: serdes@f010000 {
compatible = "ti,j721e-serdes-10g";
reg = <0x0f010000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz1 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
clock-names = "refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
assigned-clock-parents = <&k3_clks 280 1>,
<&k3_clks 280 1>,
<&k3_clks 280 1>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
};
};
pcie0_rc: pcie@f102000 {
compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x68000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&wkup_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
clock-names = "fck", "pcie_refclk";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xff>;
cdns,no-bar-match-nbits = <64>;
vendor-id = <0x104c>;
device-id = <0xb010>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
<0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
<0 0 0 2 &pcie0_intc 0>, /* INT B */
<0 0 0 3 &pcie0_intc 0>, /* INT C */
<0 0 0 4 &pcie0_intc 0>; /* INT D */
pcie0_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>;
};
};
};
/* Main domain overrides */
&inta_main_dmss {
ti,interrupt-ranges = <7 71 21>;
};
&inta_main_dmss_csi {
ti,interrupt-ranges = <0 237 8>;
};
&main_bcdma_csi {
compatible = "ti,j722s-dmss-bcdma-csi";
reg = <0x00 0x4e230000 0x00 0x100>,
<0x00 0x4e180000 0x00 0x20000>,
<0x00 0x4e300000 0x00 0x10000>,
<0x00 0x4e100000 0x00 0x80000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss_csi>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <199>;
ti,sci-rm-range-rchan = <0x21>;
ti,sci-rm-range-tchan = <0x22>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
};
&main_conf {
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x4080 0x14>;
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x3>, /* SERDES0 lane0 select */
<0x10 0x3>; /* SERDES1 lane0 select */
};
};
&oc_sram {
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
};
&cbass_main {
ti_csi2rx1: ticsi2rx@30122000 {
compatible = "ti,j721e-csi2rx";
dmas = <&main_bcdma_csi 0 0x5100 0>, <&main_bcdma_csi 0 0x5101 0>,
<&main_bcdma_csi 0 0x5102 0>, <&main_bcdma_csi 0 0x5103 0>;
dma-names = "rx0", "rx1", "rx2", "rx3";
reg = <0x00 0x30122000 0x00 0x1000>;
power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx1: csi-bridge@30121000 {
compatible = "cdns,csi2rx";
reg = <0x00 0x30121000 0x00 0x1000>;
clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>,
<&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy1>;
phy-names = "dphy";
power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi1_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi1_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi1_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi1_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi1_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
ti_csi2rx2: ticsi2rx@30142000 {
compatible = "ti,j721e-csi2rx";
dmas = <&main_bcdma_csi 0 0x5200 0>, <&main_bcdma_csi 0 0x5201 0>,
<&main_bcdma_csi 0 0x5202 0>, <&main_bcdma_csi 0 0x5203 0>;
dma-names = "rx0", "rx1", "rx2", "rx3";
reg = <0x00 0x30142000 0x00 0x1000>;
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx2: csi-bridge@30141000 {
compatible = "cdns,csi2rx";
reg = <0x00 0x30141000 0x00 0x1000>;
clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>,
<&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy2>;
phy-names = "dphy";
power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi2_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi2_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi2_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi2_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
ti_csi2rx3: ticsi2rx@30162000 {
compatible = "ti,j721e-csi2rx";
dmas = <&main_bcdma_csi 0 0x5300 0>, <&main_bcdma_csi 0 0x5301 0>,
<&main_bcdma_csi 0 0x5302 0>, <&main_bcdma_csi 0 0x5303 0>;
dma-names = "rx0", "rx1";
reg = <0x00 0x30162000 0x00 0x1000>;
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx3: csi-bridge@30161000 {
compatible = "cdns,csi2rx";
reg = <0x00 0x30161000 0x00 0x1000>;
clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>,
<&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy3>;
phy-names = "dphy";
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi3_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi3_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi3_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi3_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi3_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy1: phy@30130000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30130000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
dphy2: phy@30150000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30150000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
dphy3: phy@30170000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30170000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_r5fss0: r5fss@78400000 {
compatible = "ti,am62-r5fss";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x78400000 0x00 0x78400000 0x8000>,
<0x78500000 0x00 0x78500000 0x8000>;
power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
main_r5fss0_core0: r5f@78400000 {
compatible = "ti,am62-r5f";
reg = <0x78400000 0x00008000>,
<0x78500000 0x00008000>;
reg-names = "atcm", "btcm";
ti,sci = <&dmsc>;
ti,sci-dev-id = <262>;
ti,sci-proc-ids = <0x04 0xff>;
resets = <&k3_reset 262 1>;
firmware-name = "j722s-main-r5f0_0-fw";
ti,atcm-enable = <1>;
ti,btcm-enable = <1>;
ti,loczrama = <1>;
};
};
c7x_0: dsp@7e000000 {
compatible = "ti,am62a-c7xv-dsp";
reg = <0x00 0x7e000000 0x00 0x00200000>;
reg-names = "l2sram";
ti,sci = <&dmsc>;
ti,sci-dev-id = <208>;
ti,sci-proc-ids = <0x30 0xff>;
resets = <&k3_reset 208 1>;
firmware-name = "j722s-c71_0-fw";
status = "disabled";
};
c7x_1: dsp@7e200000 {
compatible = "ti,am62a-c7xv-dsp";
reg = <0x00 0x7e200000 0x00 0x00200000>;
reg-names = "l2sram";
ti,sci = <&dmsc>;
ti,sci-dev-id = <268>;
ti,sci-proc-ids = <0x31 0xff>;
resets = <&k3_reset 268 1>;
firmware-name = "j722s-c71_1-fw";
status = "disabled";
};
e5010: e5010@fd20000 {
compatible = "img,e5010-jpeg-enc";
reg = <0x00 0xfd20000 0x00 0x100>,
<0x00 0xfd20200 0x00 0x200>;
reg-names = "regjasper", "regmmu";
clocks = <&k3_clks 201 0>;
clock-names = "core_clk";
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
/* MCU domain overrides */
&mcu_r5fss0_core0 {
firmware-name = "j722s-mcu-r5f0_0-fw";
};
/* Wakeup domain overrides */
&wkup_r5fss0_core0 {
firmware-name = "j722s-wkup-r5f0_0-fw";
};
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