summaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/mpc5121.dtsi
blob: 2c0e1552d20bb9a410ab6c27762d676e6e7f5b9e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
/*
 * base MPC5121 Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <dt-bindings/clock/mpc512x-clock.h>

/dts-v1/;

/ {
	model = "mpc5121";
	compatible = "fsl,mpc5121";
	#address-cells = <1>;
	#size-cells = <1>;
        interrupt-parent = <&ipic>;

	aliases {
		ethernet0 = &eth0;
		pci = &pci;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5121@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	/* 32 bytes */
			i-cache-line-size = <0x20>;	/* 32 bytes */
			d-cache-size = <0x8000>;	/* L1, 32K */
			i-cache-size = <0x8000>;	/* L1, 32K */
			timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
			bus-frequency = <198000000>;	/* 198 MHz csb bus */
			clock-frequency = <396000000>;	/* 396 MHz ppc core */
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	/* 256MB at 0 */
	};

	mbx@20000000 {
		compatible = "fsl,mpc5121-mbx";
		reg = <0x20000000 0x4000>;
		interrupts = <66 0x8>;
		clocks = <&clks MPC512x_CLK_MBX_BUS>,
			 <&clks MPC512x_CLK_MBX_3D>,
			 <&clks MPC512x_CLK_MBX>;
		clock-names = "mbx-bus", "mbx-3d", "mbx";
	};

	sram@30000000 {
		compatible = "fsl,mpc5121-sram";
		reg = <0x30000000 0x20000>;	/* 128K at 0x30000000 */
	};

	nfc@40000000 {
		compatible = "fsl,mpc5121-nfc";
		reg = <0x40000000 0x100000>;	/* 1M at 0x40000000 */
		interrupts = <6 8>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&clks MPC512x_CLK_NFC>;
		clock-names = "ipg";
	};

	localbus@80000020 {
		compatible = "fsl,mpc5121-localbus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <0x80000020 0x40>;
		interrupts = <7 0x8>;
		ranges = <0x0 0x0 0xfc000000 0x04000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		osc: osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <33000000>;
		};
	};

	soc@80000000 {
		compatible = "fsl,mpc5121-immr";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x80000000 0x400000>;
		reg = <0x80000000 0x400000>;
		bus-frequency = <66000000>;	/* 66 MHz ips bus */


		/*
		 * IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@c00 {
			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0xc00 0x100>;
		};

		/* Watchdog timer */
		wdt@900 {
			compatible = "fsl,mpc5121-wdt";
			reg = <0x900 0x100>;
		};

		/* Real time clock */
		rtc@a00 {
			compatible = "fsl,mpc5121-rtc";
			reg = <0xa00 0x100>;
			interrupts = <79 0x8 80 0x8>;
		};

		/* Reset module */
		reset@e00 {
			compatible = "fsl,mpc5121-reset";
			reg = <0xe00 0x100>;
		};

		/* Clock control */
		clks: clock@f00 {
			compatible = "fsl,mpc5121-clock";
			reg = <0xf00 0x100>;
			#clock-cells = <1>;
			clocks = <&osc>;
			clock-names = "osc";
		};

		/* Power Management Controller */
		pmc@1000{
			compatible = "fsl,mpc5121-pmc";
			reg = <0x1000 0x100>;
			interrupts = <83 0x8>;
		};

		gpio@1100 {
			compatible = "fsl,mpc5121-gpio";
			reg = <0x1100 0x100>;
			interrupts = <78 0x8>;
		};

		can@1300 {
			compatible = "fsl,mpc5121-mscan";
			reg = <0x1300 0x80>;
			interrupts = <12 0x8>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN0_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		can@1380 {
			compatible = "fsl,mpc5121-mscan";
			reg = <0x1380 0x80>;
			interrupts = <13 0x8>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN1_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		sdhc@1500 {
			compatible = "fsl,mpc5121-sdhc";
			reg = <0x1500 0x100>;
			interrupts = <8 0x8>;
			dmas = <&dma0 30>;
			dma-names = "rx-tx";
			clocks = <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SDHC>;
			clock-names = "ipg", "per";
		};

		i2c@1700 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1700 0x20>;
			interrupts = <9 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2c@1720 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1720 0x20>;
			interrupts = <10 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2c@1740 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
			reg = <0x1740 0x20>;
			interrupts = <11 0x8>;
			clocks = <&clks MPC512x_CLK_I2C>;
			clock-names = "ipg";
		};

		i2ccontrol@1760 {
			compatible = "fsl,mpc5121-i2c-ctrl";
			reg = <0x1760 0x8>;
		};

		axe@2000 {
			compatible = "fsl,mpc5121-axe";
			reg = <0x2000 0x100>;
			interrupts = <42 0x8>;
			clocks = <&clks MPC512x_CLK_AXE>;
			clock-names = "ipg";
		};

		display@2100 {
			compatible = "fsl,mpc5121-diu";
			reg = <0x2100 0x100>;
			interrupts = <64 0x8>;
			clocks = <&clks MPC512x_CLK_DIU>;
			clock-names = "ipg";
		};

		can@2300 {
			compatible = "fsl,mpc5121-mscan";
			reg = <0x2300 0x80>;
			interrupts = <90 0x8>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN2_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		can@2380 {
			compatible = "fsl,mpc5121-mscan";
			reg = <0x2380 0x80>;
			interrupts = <91 0x8>;
			clocks = <&clks MPC512x_CLK_BDLC>,
				 <&clks MPC512x_CLK_IPS>,
				 <&clks MPC512x_CLK_SYS>,
				 <&clks MPC512x_CLK_REF>,
				 <&clks MPC512x_CLK_MSCAN3_MCLK>;
			clock-names = "ipg", "ips", "sys", "ref", "mclk";
		};

		viu@2400 {
			compatible = "fsl,mpc5121-viu";
			reg = <0x2400 0x400>;
			interrupts = <67 0x8>;
			clocks = <&clks MPC512x_CLK_VIU>;
			clock-names = "ipg";
		};

		mdio@2800 {
			compatible = "fsl,mpc5121-fec-mdio";
			reg = <0x2800 0x800>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&clks MPC512x_CLK_FEC>;
			clock-names = "per";
		};

		eth0: ethernet@2800 {
			device_type = "network";
			compatible = "fsl,mpc5121-fec";
			reg = <0x2800 0x800>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <4 0x8>;
			clocks = <&clks MPC512x_CLK_FEC>;
			clock-names = "per";
		};

		/* USB1 using external ULPI PHY */
		usb@3000 {
			compatible = "fsl,mpc5121-usb2-dr";
			reg = <0x3000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <43 0x8>;
			dr_mode = "otg";
			phy_type = "ulpi";
			clocks = <&clks MPC512x_CLK_USB1>;
			clock-names = "ipg";
		};

		/* USB0 using internal UTMI PHY */
		usb@4000 {
			compatible = "fsl,mpc5121-usb2-dr";
			reg = <0x4000 0x600>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <44 0x8>;
			dr_mode = "otg";
			phy_type = "utmi_wide";
			clocks = <&clks MPC512x_CLK_USB2>;
			clock-names = "ipg";
		};

		/* IO control */
		ioctl@a000 {
			compatible = "fsl,mpc5121-ioctl";
			reg = <0xA000 0x1000>;
		};

		/* LocalPlus controller */
		lpc@10000 {
			compatible = "fsl,mpc5121-lpc";
			reg = <0x10000 0x200>;
		};

		pata@10200 {
			compatible = "fsl,mpc5121-pata";
			reg = <0x10200 0x100>;
			interrupts = <5 0x8>;
			clocks = <&clks MPC512x_CLK_PATA>;
			clock-names = "ipg";
		};

		/* 512x PSCs are not 52xx PSC compatible */

		/* PSC0 */
		psc@11000 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11000 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC0>,
				 <&clks MPC512x_CLK_PSC0_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC1 */
		psc@11100 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11100 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC1>,
				 <&clks MPC512x_CLK_PSC1_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC2 */
		psc@11200 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11200 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC2>,
				 <&clks MPC512x_CLK_PSC2_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC3 */
		psc@11300 {
			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
			reg = <0x11300 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC3>,
				 <&clks MPC512x_CLK_PSC3_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC4 */
		psc@11400 {
			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
			reg = <0x11400 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC4>,
				 <&clks MPC512x_CLK_PSC4_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC5 */
		psc@11500 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11500 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC5>,
				 <&clks MPC512x_CLK_PSC5_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC6 */
		psc@11600 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11600 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC6>,
				 <&clks MPC512x_CLK_PSC6_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC7 */
		psc@11700 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11700 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC7>,
				 <&clks MPC512x_CLK_PSC7_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC8 */
		psc@11800 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11800 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC8>,
				 <&clks MPC512x_CLK_PSC8_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC9 */
		psc@11900 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11900 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC9>,
				 <&clks MPC512x_CLK_PSC9_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC10 */
		psc@11a00 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11a00 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC10>,
				 <&clks MPC512x_CLK_PSC10_MCLK>;
			clock-names = "ipg", "mclk";
		};

		/* PSC11 */
		psc@11b00 {
			compatible = "fsl,mpc5121-psc";
			reg = <0x11b00 0x100>;
			interrupts = <40 0x8>;
			fsl,rx-fifo-size = <16>;
			fsl,tx-fifo-size = <16>;
			clocks = <&clks MPC512x_CLK_PSC11>,
				 <&clks MPC512x_CLK_PSC11_MCLK>;
			clock-names = "ipg", "mclk";
		};

		pscfifo@11f00 {
			compatible = "fsl,mpc5121-psc-fifo";
			reg = <0x11f00 0x100>;
			interrupts = <40 0x8>;
			clocks = <&clks MPC512x_CLK_PSC_FIFO>;
			clock-names = "ipg";
		};

		dma0: dma@14000 {
			compatible = "fsl,mpc5121-dma";
			reg = <0x14000 0x1800>;
			interrupts = <65 0x8>;
		};
	};

	pci: pci@80008500 {
		compatible = "fsl,mpc5121-pci";
		device_type = "pci";
		interrupts = <1 0x8>;
		clock-frequency = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		clocks = <&clks MPC512x_CLK_PCI>;
		clock-names = "ipg";

		reg = <0x80008500 0x100	/* internal registers */
		       0x80008300 0x8>;	/* config space access registers */
		bus-range = <0x0 0x0>;
		ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
	};
};