1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
/*
* drivers/video/tegra/dc/clock.c
*
* Copyright (C) 2010 Google, Inc.
*
* Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/err.h>
#include <linux/types.h>
#include <linux/clk.h>
#include <mach/clk.h>
#include <mach/dc.h>
#include "dc_reg.h"
#include "dc_priv.h"
unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
{
unsigned long rate;
unsigned long div;
rate = tegra_dc_clk_get_rate(dc);
div = DIV_ROUND_CLOSEST(rate * 2, pclk);
if (div < 2)
return 0;
return rate * 2 / div;
}
unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
{
unsigned long rate;
unsigned long div;
rate = clk_get_rate(parent);
div = DIV_ROUND_CLOSEST(rate * 2, pclk);
if (div < 2)
return 0;
return rate * 2 / div;
}
void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
{
int pclk;
if (dc->out_ops->setup_clk)
pclk = dc->out_ops->setup_clk(dc, clk);
else
pclk = 0;
WARN_ONCE(!pclk, "pclk is 0\n");
tegra_dvfs_set_rate(clk, pclk);
}
|
