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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#ifndef __DT_BINDINGS_CLOCK_IMX_H
#define __DT_BINDINGS_CLOCK_IMX_H
/* SCU Clocks */
#define IMX_CLK_DUMMY 0
/* CPU */
#define IMX_A35_CLK 1
#define IMX_24MHZ 4
#define IMX_24MHZ 4
/* LSIO SS */
#define IMX_LSIO_MEM_CLK 2
#define IMX_LSIO_BUS_CLK 3
#define IMX_LSIO_PWM0_CLK 10
#define IMX_LSIO_PWM1_CLK 11
#define IMX_LSIO_PWM2_CLK 12
#define IMX_LSIO_PWM3_CLK 13
#define IMX_LSIO_PWM4_CLK 14
#define IMX_LSIO_PWM5_CLK 15
#define IMX_LSIO_PWM6_CLK 16
#define IMX_LSIO_PWM7_CLK 17
#define IMX_LSIO_GPT0_CLK 18
#define IMX_LSIO_GPT1_CLK 19
#define IMX_LSIO_GPT2_CLK 20
#define IMX_LSIO_GPT3_CLK 21
#define IMX_LSIO_GPT4_CLK 22
#define IMX_LSIO_FSPI0_CLK 23
#define IMX_LSIO_FSPI1_CLK 24
/* Connectivity SS */
#define IMX_CONN_AXI_CLK_ROOT 30
#define IMX_CONN_AHB_CLK_ROOT 31
#define IMX_CONN_IPG_CLK_ROOT 32
#define IMX_CONN_PLL0_CLK 33
#define IMX_CONN_PLL1_CLK 34
#define IMX_CONN_SDHC0_CLK 40
#define IMX_CONN_SDHC1_CLK 41
#define IMX_CONN_SDHC2_CLK 42
#define IMX_CONN_ENET0_ROOT_CLK 43
#define IMX_CONN_ENET0_BYPASS_CLK 44
#define IMX_CONN_ENET0_RGMII_RX_CLK 45
#define IMX_CONN_ENET1_ROOT_CLK 46
#define IMX_CONN_ENET1_BYPASS_CLK 47
#define IMX_CONN_ENET1_RGMII_RX_CLK 48
#define IMX_CONN_GPMI_BCH_IO_CLK 49
#define IMX_CONN_GPMI_BCH_CLK 50
#define IMX_CONN_USB2_ACLK 51
#define IMX_CONN_USB2_BUS_CLK 52
#define IMX_CONN_USB2_LPM_CLK 53
#define IMX_CONN_ENET0_REF_DIV 54
#define IMX_CONN_ENET0_RGMII_TXC_SEL 55
#define IMX_CONN_ENET1_REF_DIV 56
#define IMX_CONN_ENET1_RGMII_TXC_SEL 57
#define IMX_CONN_ENET0_RMII_REF_50MHZ_CLK 58
#define IMX_CONN_ENET1_RMII_REF_50MHZ_CLK 59
/* HSIO SS */
#define IMX_HSIO_AXI_CLK 60
#define IMX_HSIO_PER_CLK 61
/* Display controller SS */
#define IMX_DC_AXI_EXT_CLK 70
#define IMX_DC_AXI_INT_CLK 71
#define IMX_DC_CFG_CLK 72
#define IMX_DC0_PLL0_CLK 80
#define IMX_DC0_PLL1_CLK 81
#define IMX_DC0_DISP0_CLK 82
#define IMX_DC0_DISP1_CLK 83
#define IMX_DC0_BYPASS0_CLK 84
#define IMX_DC0_BYPASS1_CLK 85
/* MIPI-LVDS SS */
#define IMX_MIPI_IPG_CLK 90
#define IMX_MIPI1_DSI_TX_ESC_CLK 98
#define IMX_MIPI1_DSI_RX_ESC_CLK 99
#define IMX_MIPI0_PIXEL_CLK 100
#define IMX_MIPI0_BYPASS_CLK 101
#define IMX_LVDS0_PIXEL_CLK 102
#define IMX_LVDS0_BYPASS_CLK 103
#define IMX_LVDS0_PHY_CLK 104
#define IMX_MIPI0_I2C0_CLK 105
#define IMX_MIPI0_I2C1_CLK 106
#define IMX_MIPI0_PWM0_CLK 107
#define IMX_MIPI1_PIXEL_CLK 108
#define IMX_MIPI1_BYPASS_CLK 109
#define IMX_LVDS1_PIXEL_CLK 110
#define IMX_LVDS1_BYPASS_CLK 111
#define IMX_LVDS1_PHY_CLK 112
#define IMX_MIPI1_I2C0_CLK 113
#define IMX_MIPI1_I2C1_CLK 114
#define IMX_MIPI1_PWM0_CLK 115
#define IMX_MIPI0_DSI_TX_ESC_CLK 116
#define IMX_MIPI0_DSI_RX_ESC_CLK 117
#define IMX_MIPI0_DSI_PHY_CLK 118
/* IMG SS */
#define IMX_IMG_AXI_CLK 120
#define IMX_IMG_IPG_CLK 121
#define IMX_IMG_PXL_CLK 122
/* MIPI-CSI SS */
#define IMX_CSI0_CORE_CLK 130
#define IMX_CSI0_ESC_CLK 131
#define IMX_CSI0_PWM0_CLK 132
#define IMX_CSI0_I2C0_CLK 133
#define IMX_CSI1_CORE_CLK 134
#define IMX_CSI1_ESC_CLK 135
#define IMX_CSI1_PWM0_CLK 136
#define IMX_CSI1_I2C0_CLK 137
/* PARALLER CSI SS */
#define IMX_PARALLEL_DPLL_CLK 140
#define IMX_PARALLEL_PER_DIV_CLK 141
#define IMX_PARALLEL_MCLK_DIV_CLK 142
/* VPU SS */
#define IMX_VPU_ENC_CLK 150
#define IMX_VPU_DEC_CLK 151
/* GPU SS */
#define IMX_GPU0_CORE_CLK 160
#define IMX_GPU0_SHADER_CLK 161
/* ADMA SS */
#define IMX_ADMA_IPG_CLK_ROOT 165
#define IMX_ADMA_UART0_CLK 170
#define IMX_ADMA_UART1_CLK 171
#define IMX_ADMA_UART2_CLK 172
#define IMX_ADMA_UART3_CLK 173
#define IMX_ADMA_SPI0_CLK 174
#define IMX_ADMA_SPI1_CLK 175
#define IMX_ADMA_SPI2_CLK 176
#define IMX_ADMA_SPI3_CLK 177
#define IMX_ADMA_CAN0_CLK 178
#define IMX_ADMA_CAN1_CLK 179
#define IMX_ADMA_CAN2_CLK 180
#define IMX_ADMA_I2C0_CLK 181
#define IMX_ADMA_I2C1_CLK 182
#define IMX_ADMA_I2C2_CLK 183
#define IMX_ADMA_I2C3_CLK 184
#define IMX_ADMA_FTM0_CLK 185
#define IMX_ADMA_FTM1_CLK 186
#define IMX_ADMA_ADC0_CLK 187
#define IMX_ADMA_PWM_CLK 188
#define IMX_ADMA_LCD_CLK 189
#define IMX_ADMA_AUD_PLL0 191
#define IMX_ADMA_AUD_PLL1 192
#define IMX_ADMA_AUD_PLL_DIV_CLK0_CLK 193
#define IMX_ADMA_AUD_PLL_DIV_CLK1_CLK 194
#define IMX_ADMA_AUD_REC_CLK0_CLK 195
#define IMX_ADMA_AUD_REC_CLK1_CLK 196
/* CM40 SS */
#define IMX_CM40_IPG_CLK 200
#define IMX_CM40_I2C_DIV 205
#define IMX_SCU_CLK_END 220
#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
#define IMX_ADMA_ACM_AUD_CLK0_CLK 1
#define IMX_ADMA_ACM_AUD_CLK1_SEL 2
#define IMX_ADMA_ACM_AUD_CLK1_CLK 3
#define IMX_ADMA_ACM_MCLKOUT0_SEL 4
#define IMX_ADMA_ACM_MCLKOUT1_SEL 5
#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 6
#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 7
#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 8
#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 9
#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 10
#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 11
#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 12
#define IMX_ADMA_ACM_SAI0_MCLK_SEL 13
#define IMX_ADMA_ACM_SAI1_MCLK_SEL 14
#define IMX_ADMA_ACM_SAI2_MCLK_SEL 15
#define IMX_ADMA_ACM_SAI3_MCLK_SEL 16
#define IMX_ADMA_ACM_SAI4_MCLK_SEL 17
#define IMX_ADMA_ACM_SAI5_MCLK_SEL 18
#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 19
#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 20
#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 21
#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 22
#define IMX_ADMA_EXT_AUD_MCLK0 23
#define IMX_ADMA_EXT_AUD_MCLK1 24
#define IMX_ADMA_ESAI0_RX_CLK 25
#define IMX_ADMA_ESAI0_RX_HF_CLK 26
#define IMX_ADMA_ESAI0_TX_CLK 27
#define IMX_ADMA_ESAI0_TX_HF_CLK 28
#define IMX_ADMA_SPDIF0_RX 29
#define IMX_ADMA_SAI0_RX_BCLK 30
#define IMX_ADMA_SAI0_TX_BCLK 31
#define IMX_ADMA_SAI1_RX_BCLK 32
#define IMX_ADMA_SAI1_TX_BCLK 33
#define IMX_ADMA_SAI2_RX_BCLK 34
#define IMX_ADMA_SAI3_RX_BCLK 35
#define IMX_ADMA_SAI4_RX_BCLK 36
#define IMX_ADMA_ACM_CLK_END 37
/* LPCG clocks */
/* LSIO SS LPCG */
#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
#define IMX_LSIO_LPCG_FSPI0_HCLK 65
#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
#define IMX_LSIO_LPCG_FSPI1_HCLK 69
#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
#define IMX_LSIO_LPCG_CLK_END 73
/* Connectivity SS LPCG */
#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
#define IMX_CONN_LPCG_SDHC0_PER_CLK 1
#define IMX_CONN_LPCG_SDHC0_HCLK 2
#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
#define IMX_CONN_LPCG_SDHC1_PER_CLK 4
#define IMX_CONN_LPCG_SDHC1_HCLK 5
#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
#define IMX_CONN_LPCG_SDHC2_PER_CLK 7
#define IMX_CONN_LPCG_SDHC2_HCLK 8
#define IMX_CONN_LPCG_GPMI_APB_CLK 9
#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
#define IMX_CONN_LPCG_GPMI_BCH_CLK 12
#define IMX_CONN_LPCG_APBHDMA_CLK 13
#define IMX_CONN_LPCG_ENET0_TIMER_CLK 14
#define IMX_CONN_LPCG_ENET0_RGMII_TXC_CLK 15
#define IMX_CONN_LPCG_ENET0_AHB_CLK 16
#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
#define IMX_CONN_LPCG_ENET0_IPG_CLK 18
#define IMX_CONN_LPCG_ENET1_TIMER_CLK 19
#define IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK 20
#define IMX_CONN_LPCG_ENET1_AHB_CLK 21
#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
#define IMX_CONN_LPCG_ENET1_IPG_CLK 23
#define IMX_CONN_LPCG_USB2_PHY_IPG_CLK 24
#define IMX_CONN_LPCG_USB2_AHB_CLK 25
#define IMX_CONN_LPCG_ENET0_TXC_SAMPLING_CLK 26
#define IMX_CONN_LPCG_ENET1_TXC_SAMPLING_CLK 27
#define IMX_CONN_LPCG_CLK_END 30
/* ADMA SS LPCG */
#define IMX_ADMA_LPCG_UART0_IPG_CLK 0
#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
#define IMX_ADMA_LPCG_UART1_IPG_CLK 2
#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
#define IMX_ADMA_LPCG_UART2_IPG_CLK 4
#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
#define IMX_ADMA_LPCG_UART3_IPG_CLK 6
#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
#define IMX_ADMA_LPCG_SPI0_CLK 12
#define IMX_ADMA_LPCG_SPI1_CLK 13
#define IMX_ADMA_LPCG_SPI2_CLK 14
#define IMX_ADMA_LPCG_SPI3_CLK 15
#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
#define IMX_ADMA_LPCG_I2C0_CLK 25
#define IMX_ADMA_LPCG_I2C1_CLK 26
#define IMX_ADMA_LPCG_I2C2_CLK 27
#define IMX_ADMA_LPCG_I2C3_CLK 28
#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
#define IMX_ADMA_LPCG_FTM0_CLK 33
#define IMX_ADMA_LPCG_FTM1_CLK 34
#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
#define IMX_ADMA_LPCG_PWM_HI_CLK 37
#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
#define IMX_ADMA_LPCG_LCD_APB_CLK 40
#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
#define IMX_ADMA_LPCG_AMIX_IPG_CLK 45
#define IMX_ADMA_LPCG_ESAI_0_IPG_CLK 46
#define IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK 47
#define IMX_ADMA_LPCG_SAI_0_IPG_CLK 48
#define IMX_ADMA_LPCG_SAI_0_MCLK 49
#define IMX_ADMA_LPCG_SAI_1_IPG_CLK 50
#define IMX_ADMA_LPCG_SAI_1_MCLK 51
#define IMX_ADMA_LPCG_SAI_2_IPG_CLK 52
#define IMX_ADMA_LPCG_SAI_2_MCLK 53
#define IMX_ADMA_LPCG_SAI_3_IPG_CLK 54
#define IMX_ADMA_LPCG_SAI_3_MCLK 55
#define IMX_ADMA_LPCG_SAI_4_IPG_CLK 56
#define IMX_ADMA_LPCG_SAI_4_MCLK 57
#define IMX_ADMA_LPCG_SAI_5_IPG_CLK 58
#define IMX_ADMA_LPCG_SAI_5_MCLK 59
#define IMX_ADMA_LPCG_MQS_IPG_CLK 60
#define IMX_ADMA_LPCG_MQS_MCLK 61
#define IMX_ADMA_LPCG_GPT5_IPG_CLK 62
#define IMX_ADMA_LPCG_GPT5_CLKIN 63
#define IMX_ADMA_LPCG_GPT6_IPG_CLK 64
#define IMX_ADMA_LPCG_GPT6_CLKIN 65
#define IMX_ADMA_LPCG_GPT7_IPG_CLK 66
#define IMX_ADMA_LPCG_GPT7_CLKIN 67
#define IMX_ADMA_LPCG_GPT8_IPG_CLK 68
#define IMX_ADMA_LPCG_GPT8_CLKIN 69
#define IMX_ADMA_LPCG_GPT9_IPG_CLK 70
#define IMX_ADMA_LPCG_GPT9_CLKIN 71
#define IMX_ADMA_LPCG_GPT10_IPG_CLK 72
#define IMX_ADMA_LPCG_GPT10_CLKIN 73
#define IMX_ADMA_LPCG_MCLKOUT0 74
#define IMX_ADMA_LPCG_MCLKOUT1 75
#define IMX_ADMA_LPCG_SPDIF_0_TX_CLK 76
#define IMX_ADMA_LPCG_SPDIF_0_GCLKW 77
#define IMX_ADMA_LPCG_ASRC_0_IPG_CLK 79
#define IMX_ADMA_LPCG_ASRC_1_IPG_CLK 80
#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK 81
#define IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK 82
#define IMX_ADMA_LPCG_AUD_REC_CLK0_CLK 83
#define IMX_ADMA_LPCG_AUD_REC_CLK1_CLK 84
#define IMX_ADMA_LPCG_CLK_END 85
/* CM40 SS LPCG */
#define IMX_CM40_LPCG_I2C_IPG_CLK 0
#define IMX_CM40_LPCG_I2C_CLK 1
#define IMX_CM40_LPCG_CLK_END 2
/* HSIO SS LPCG */
#define IMX_HSIO_LPCG_PCIEA_MSTR_AXI_CLK 0
#define IMX_HSIO_LPCG_PCIEA_SLV_AXI_CLK 1
#define IMX_HSIO_LPCG_PCIEA_DBI_AXI_CLK 2
#define IMX_HSIO_LPCG_PCIEB_MSTR_AXI_CLK 3
#define IMX_HSIO_LPCG_PCIEB_SLV_AXI_CLK 4
#define IMX_HSIO_LPCG_PCIEB_DBI_AXI_CLK 5
#define IMX_HSIO_LPCG_SATA_CLK 6
#define IMX_HSIO_LPCG_PHYX2_PCLK_0 7
#define IMX_HSIO_LPCG_PHYX2_PCLK_1 8
#define IMX_HSIO_LPCG_PHYX2_APB_0_CLK 9
#define IMX_HSIO_LPCG_PHYX2_APB_1_CLK 10
#define IMX_HSIO_LPCG_PHYX1_PCLK 11
#define IMX_HSIO_LPCG_PHYX1_EPCS_TX_CLK 12
#define IMX_HSIO_LPCG_PHYX1_EPCS_RX_CLK 13
#define IMX_HSIO_LPCG_PHYX1_APB_CLK 14
#define IMX_HSIO_LPCG_PHYX2_PER_CLK 15
#define IMX_HSIO_LPCG_PHYX1_PER_CLK 16
#define IMX_HSIO_LPCG_PCIEA_PER_CLK 17
#define IMX_HSIO_LPCG_PCIEB_PER_CLK 18
#define IMX_HSIO_LPCG_SATA_PER_CLK 19
#define IMX_HSIO_LPCG_MISC_PER_CLK 20
#define IMX_HSIO_LPCG_GPIO_PER_CLK 21
#define IMX_HSIO_LPCG_CLK_END 22
/* IMAGE SS LPCG */
#define IMX_IMG_LPCG_PDMA0_CLK 0
#define IMX_IMG_LPCG_PDMA1_CLK 1
#define IMX_IMG_LPCG_PDMA2_CLK 2
#define IMX_IMG_LPCG_PDMA3_CLK 3
#define IMX_IMG_LPCG_PDMA4_CLK 4
#define IMX_IMG_LPCG_PDMA5_CLK 5
#define IMX_IMG_LPCG_PDMA6_CLK 6
#define IMX_IMG_LPCG_PDMA7_CLK 7
#define IMX_IMG_LPCG_CSI0_PXL_LINK_CLK 8
#define IMX_IMG_LPCG_CSI1_PXL_LINK_CLK 9
#define IMX_IMG_LPCG_CLK_END 10
/* CSI SS LPCG */
#define IMX_CSI_LPCG_CSI0_CORE_CLK 0
#define IMX_CSI_LPCG_CSI0_ESC_CLK 1
#define IMX_CSI_LPCG_CSI0_I2C0_CLK 2
#define IMX_CSI_LPCG_CSI0_CLK_END 3
/* CSI SS LPCG */
#define IMX_CSI_LPCG_CSI1_CORE_CLK 0
#define IMX_CSI_LPCG_CSI1_ESC_CLK 1
#define IMX_CSI_LPCG_CSI1_I2C0_CLK 2
#define IMX_CSI_LPCG_CSI1_CLK_END 3
/* Parallel Interface SS LPCG */
#define IMX_PI_LPCG_PI0_PIXEL_CLK 0
#define IMX_PI_LPCG_PI0_IPG_CLK 1
#define IMX_PI_LPCG_PI0_MISC_CLK 2
#define IMX_PI_LPCG_CLK_END 3
/* DC SS LPCG */
#define IMX_DC0_LPCG_PRG0_RTRAM_CLK 0
#define IMX_DC0_LPCG_PRG0_APB_CLK 1
#define IMX_DC0_LPCG_PRG1_RTRAM_CLK 2
#define IMX_DC0_LPCG_PRG1_APB_CLK 3
#define IMX_DC0_LPCG_PRG2_RTRAM_CLK 4
#define IMX_DC0_LPCG_PRG2_APB_CLK 5
#define IMX_DC0_LPCG_PRG3_RTRAM_CLK 6
#define IMX_DC0_LPCG_PRG3_APB_CLK 7
#define IMX_DC0_LPCG_PRG4_RTRAM_CLK 8
#define IMX_DC0_LPCG_PRG4_APB_CLK 9
#define IMX_DC0_LPCG_PRG5_RTRAM_CLK 10
#define IMX_DC0_LPCG_PRG5_APB_CLK 11
#define IMX_DC0_LPCG_PRG6_RTRAM_CLK 12
#define IMX_DC0_LPCG_PRG6_APB_CLK 13
#define IMX_DC0_LPCG_PRG7_RTRAM_CLK 14
#define IMX_DC0_LPCG_PRG7_APB_CLK 15
#define IMX_DC0_LPCG_PRG8_RTRAM_CLK 16
#define IMX_DC0_LPCG_PRG8_APB_CLK 17
#define IMX_DC0_LPCG_DPR0_APB_CLK 18
#define IMX_DC0_LPCG_DPR0_B_CLK 19
#define IMX_DC0_LPCG_DPR1_APB_CLK 20
#define IMX_DC0_LPCG_DPR1_B_CLK 21
#define IMX_DC0_LPCG_RTRAM0_CLK 22
#define IMX_DC0_LPCG_RTRAM1_CLK 23
#define IMX_DC0_LPCG_CLK_END 24
/* MIPI LVDS LPCG */
#define IMX_MIPI0_LPCG_I2C0_CLK 0
#define IMX_MIPI0_LPCG_I2C1_CLK 1
#define IMX_MIPI0_LPCG_I2C0_IPG_S_CLK 2
#define IMX_MIPI0_LPCG_I2C0_IPG_CLK 3
#define IMX_MIPI0_LPCG_I2C1_IPG_S_CLK 4
#define IMX_MIPI0_LPCG_I2C1_IPG_CLK 5
#define IMX_MIPI0_LPCG_PWM_IPG_S_CLK 6
#define IMX_MIPI0_LPCG_PWM_IPG_CLK 7
#define IMX_MIPI0_LPCG_PWM_32K_CLK 8
#define IMX_MIPI0_LPCG_PWM_CLK 9
#define IMX_MIPI0_LPCG_GPIO_IPG_CLK 10
#define IMX_MIPI0_LPCG_LIS_IPG_CLK 11
#define IMX_MIPI0_LPCG_CLK_END 12
#define IMX_MIPI1_LPCG_I2C0_CLK 0
#define IMX_MIPI1_LPCG_I2C1_CLK 1
#define IMX_MIPI1_LPCG_I2C0_IPG_S_CLK 2
#define IMX_MIPI1_LPCG_I2C0_IPG_CLK 3
#define IMX_MIPI1_LPCG_I2C1_IPG_S_CLK 4
#define IMX_MIPI1_LPCG_I2C1_IPG_CLK 5
#define IMX_MIPI1_LPCG_PWM_IPG_S_CLK 6
#define IMX_MIPI1_LPCG_PWM_IPG_CLK 7
#define IMX_MIPI1_LPCG_PWM_32K_CLK 8
#define IMX_MIPI1_LPCG_PWM_CLK 9
#define IMX_MIPI1_LPCG_GPIO_IPG_CLK 10
#define IMX_MIPI1_LPCG_LIS_IPG_CLK 11
#define IMX_MIPI1_LPCG_CLK_END 12
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
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