1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
/*
* arch/arm/mach-tegra/cpuidle.h
*
* Declarations for power state transition code
*
* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_CPUIDLE_H
#define __MACH_TEGRA_CPUIDLE_H
#include <linux/cpuidle.h>
#ifdef CONFIG_PM_SLEEP
#define TEGRA_CPUIDLE_FORCE_DO_CLKGT_VMIN 0x1
#define TEGRA_CPUIDLE_FORCE_NO_CLKGT_VMIN 0x2
/*
* Available tegra cpuidle states.
* Should not exceed CPUIDLE_STATE_MAX
*/
enum tegra_cpuidle_states {
CPUIDLE_STATE_CLKGATING,
CPUIDLE_STATE_POWERGATING,
CPUIDLE_STATE_MC_CLK_STOP,
CPUIDLE_MAX_STATE_NUM = CPUIDLE_STATE_MAX,
};
extern int tegra_pg_exit_latency;
extern u32 tegra_force_clkgt_at_vmin;
struct tegra_cpuidle_ops {
int (*tegra_idle_pd)(struct cpuidle_device *dev,
struct cpuidle_state *state);
void (*cpu_idle_stats_pd_ready)(unsigned int cpu);
void (*cpu_idle_stats_pd_time)(unsigned int cpu, s64 us);
bool (*pd_is_allowed)(struct cpuidle_device *dev,
struct cpuidle_state *state);
#ifdef CONFIG_DEBUG_FS
int (*pd_debug_show)(struct seq_file *s, void *data);
#endif
};
int tegra2_cpuidle_init_soc(struct tegra_cpuidle_ops *ops);
int tegra3_cpuidle_init_soc(struct tegra_cpuidle_ops *ops);
int tegra11x_cpuidle_init_soc(struct tegra_cpuidle_ops *ops);
int tegra14x_cpuidle_init_soc(struct tegra_cpuidle_ops *ops);
int tegra11_cpu_lp_idle_rate_exchange(unsigned long *rate);
int tegra11_cpu_g_idle_rate_exchange(unsigned long *rate);
int tegra14_cpu_lp_idle_rate_exchange(unsigned long *rate);
int tegra14_cpu_g_idle_rate_exchange(unsigned long *rate);
int tegra12_cpu_lp_idle_rate_exchange(unsigned long *rate);
int tegra12_cpu_g_idle_rate_exchange(unsigned long *rate);
static inline int tegra_cpuidle_init_soc(struct tegra_cpuidle_ops *ops)
{
#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
return tegra2_cpuidle_init_soc(ops);
#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
return tegra3_cpuidle_init_soc(ops);
#elif defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
defined(CONFIG_ARCH_TEGRA_12x_SOC)
return tegra11x_cpuidle_init_soc(ops);
#elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
return tegra14x_cpuidle_init_soc(ops);
#else
return 0;
#endif
}
static inline int tegra_cpu_g_idle_rate_exchange(unsigned long *rate)
{
#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
return tegra11_cpu_g_idle_rate_exchange(rate);
#elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
return tegra12_cpu_g_idle_rate_exchange(rate);
#elif defined CONFIG_ARCH_TEGRA_14x_SOC
return tegra14_cpu_g_idle_rate_exchange(rate);
#else
return -ENOSYS;
#endif
}
static inline int tegra_cpu_lp_idle_rate_exchange(unsigned long *rate)
{
#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
return tegra11_cpu_lp_idle_rate_exchange(rate);
#elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
return tegra12_cpu_lp_idle_rate_exchange(rate);
#elif defined CONFIG_ARCH_TEGRA_14x_SOC
return tegra14_cpu_lp_idle_rate_exchange(rate);
#else
return -ENOSYS;
#endif
}
static inline void tegra_pd_set_global_latency(struct cpuidle_state *state)
{
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
state->exit_latency = tegra_pg_exit_latency;
#endif
/* Tegra3 does not use global exit latency */
}
void tegra_pd_update_target_residency(struct cpuidle_state *state);
#endif /* CONFIG_PM_SLEEP */
#if defined(CONFIG_CPU_IDLE) && defined(CONFIG_PM_SLEEP)
void tegra_pd_in_idle(bool enable);
#else
static inline void tegra_pd_in_idle(bool enable) {}
#endif
#endif
|
