u-boot-toradex.git/board/toradex, branch master U-Boot bootloader for Apalis and Colibri modules board: toradex: fix tdx-cfg-block prompt buffer overflow 2026-04-13T23:42:58+00:00 Ngo Luong Thanh Tra ngotra27101996@gmail.com 2026-03-28T06:01:32+00:00 564e180d701f3946e6adc7895f2524728b985f03 Replace unbounded sprintf() with snprintf() using sizeof(message) as the bound for all prompt string assignments in get_cfgblock_interactive(), get_cfgblock_carrier_interactive(), do_cfgblock_carrier_create() and do_cfgblock_create(). The previous calls had no size limit and could overflow the CONFIG_SYS_CBSIZE-sized stack buffer if SYS_CBSIZE was configured smaller than the longest prompt string (71 bytes). Fixes: 8b6dc5d3943c ("toradex: tdx-cfg-block: Cleanup interactive cfg block creation") Signed-off-by: Ngo Luong Thanh Tra <S4210155@student.rmit.edu.au> To: u-boot@lists.denx.de 
Replace unbounded sprintf() with snprintf() using sizeof(message)
as the bound for all prompt string assignments in
get_cfgblock_interactive(), get_cfgblock_carrier_interactive(),
do_cfgblock_carrier_create() and do_cfgblock_create(). The
previous calls had no size limit and could overflow the
CONFIG_SYS_CBSIZE-sized stack buffer if SYS_CBSIZE was configured
smaller than the longest prompt string (71 bytes).

Fixes: 8b6dc5d3943c ("toradex: tdx-cfg-block: Cleanup interactive cfg block creation")
Signed-off-by: Ngo Luong Thanh Tra <S4210155@student.rmit.edu.au>
To: u-boot@lists.denx.de
imx8mp: verdin: Convert to DM_PMIC 2026-04-02T12:11:33+00:00 Peng Fan peng.fan@nxp.com 2026-03-30T14:04:04+00:00 b1e8c95e2bf59ae317c918a2424b6fc0ba96c0ef Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC handling. Changes include: - Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig. - Drop legacy SPL I2C and PMIC options. - Remove manual I2C1 pad setup and legacy power_pca9450_init() usage. - Use DM-based pmic_get() with the DT node "pmic@25". - Update PMIC register programming to use struct udevice API. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> 
Convert the board to use DM_PMIC instead of the legacy SPL I2C/PMIC
handling.

Changes include:
- Enable DM_PMIC, DM_PMIC_PCA9450, and SPL_DM_PMIC_PCA9450 in defconfig.
- Drop legacy SPL I2C and PMIC options.
- Remove manual I2C1 pad setup and legacy power_pca9450_init() usage.
- Use DM-based pmic_get() with the DT node "pmic@25".
- Update PMIC register programming to use struct udevice API.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
arm: dts: imx95-toradex-smarc: migrate to OF_UPSTREAM 2026-04-02T12:11:08+00:00 Franz Schnyder franz.schnyder@toradex.com 2026-03-30T07:59:41+00:00 417f658567035e4a839fbd73abe681cbedddce95 Allow CONFIG_OF_UPSTREAM to receive automatic device tree updates for the Toradex SMARC iMX95. Remove the now obsolete device tree files: - imx95-toradex-smarc-dev.dts - imx95-toradex-smarc.dtsi Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com> 
Allow CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the Toradex SMARC iMX95.

Remove the now obsolete device tree files:
- imx95-toradex-smarc-dev.dts
- imx95-toradex-smarc.dtsi

Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
Merge patch series "DDR configuration refactor and 16GB dual-rank support" 2026-03-23T15:19:00+00:00 Tom Rini trini@konsulko.com 2026-03-23T15:19:00+00:00 1ffc541eafc96d5eebcf837ab892dccec3b93568 Emanuele Ghidoli <ghidoliemanuele@gmail.com> says: From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> This series refactors the DDR configuration handling for the Toradex Aquila AM69 board and adds support for a 16GB dual-rank memory configuration, while changing the HW_CFG pins value to DDR configurations mapping. Link: https://lore.kernel.org/r/20260309155342.145432-1-ghidoliemanuele@gmail.com 
Emanuele Ghidoli <ghidoliemanuele@gmail.com> says:

From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

This series refactors the DDR configuration handling for the
Toradex Aquila AM69 board and adds support for a 16GB dual-rank
memory configuration, while changing the HW_CFG pins value to
DDR configurations mapping.

Link: https://lore.kernel.org/r/20260309155342.145432-1-ghidoliemanuele@gmail.com
board: toradex: aquila-am69: Add support for 16GB dual rank memory configuration 2026-03-23T15:18:56+00:00 Emanuele Ghidoli emanuele.ghidoli@toradex.com 2026-03-09T15:53:08+00:00 39e014f43a15e79b82946922ef7062ae0969ac99 Move the existing 16GB single-rank configuration to HW_CFG 0x03 and use the previous HW_CFG 0x01 value for the new 16GB dual-rank configuration. There is no hardware using the former 16GB single-rank configuration, so reuse the HW_CFG value for the new 16GB dual-rank configuration, which will be used in production. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> 
Move the existing 16GB single-rank configuration to HW_CFG 0x03 and use
the previous HW_CFG 0x01 value for the new 16GB dual-rank configuration.

There is no hardware using the former 16GB single-rank configuration,
so reuse the HW_CFG value for the new 16GB dual-rank configuration,
which will be used in production.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
board: toradex: aquila-am69: refactor memory configuration 2026-03-23T15:18:56+00:00 Emanuele Ghidoli emanuele.ghidoli@toradex.com 2026-03-09T15:53:07+00:00 f1fa4221485822317629f4d2c5d7087170915c66 The memory controller configuration doesn't depend only on the memory size, so refactor the code to use the memory configuration read from the HW_CFG pin instead of the memory size. Additionally, make use of one header file for all the memory configurations. Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> 
The memory controller configuration doesn't depend only on the memory
size, so refactor the code to use the memory configuration read from
the HW_CFG pin instead of the memory size.
Additionally, make use of one header file for all the memory
configurations.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
toradex: tdx-cfg-block: add aquila tda4 0223 pid4 2026-03-16T16:37:00+00:00 Vitor Soares vitor.soares@toradex.com 2026-02-13T12:01:59+00:00 d89dd94c0ad3f7f5cfb2fd0d3e7bf70e84e3d70d Add PID4 0223 Aquila TDA4 Octa 16GB IT to config block handling. Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> 
Add PID4 0223 Aquila TDA4 Octa 16GB IT to config block handling.

Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Merge patch series "board: k3: Sync rm-cfg with TIFS v11.02.09 firmware" 2026-03-13T20:58:17+00:00 Tom Rini trini@konsulko.com 2026-03-13T20:58:17+00:00 7403d26bea36315f2008ed3ef80125b094c0bafb Sparsh Kumar <sparsh-kumar@ti.com> says: This series updates the Resource Management (RM) configuration files for AM62 family devices to align with the TIFS v11.02.09 firmware. Background ---------- With the latest TIFS firmware (v11.02.09), an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x, am62ax, and am62px devices. This series brings the rm-cfg and tifs-rm-cfg files in sync with these firmware changes across both TI reference boards and vendor boards. These changes are backward compatible with older TIFS firmware versions. Additionally, the am62x platform was originally introduced without a tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family. This series addresses that gap and enables tifs-rm-cfg in binman for am625-sk and am62p-sk platforms. Changes ------- TI reference boards (patches 1-4): - Update rm-cfg.yaml for am62x, am62ax, am62px - Sync am62px tifs-rm-cfg.yaml with TIFS firmware template - Add missing tifs-rm-cfg.yaml for am62x - Enable tifs-rm-cfg in binman for am625-sk and am62p-sk Vendor boards (patches 5-9): - beagleplay (am62x-based) - phytec phycore_am62x - toradex verdin-am62 - phytec phycore_am62ax - toradex verdin-am62p with the required interrupt reservation. The tifs-rm-cfg.yaml files cannot be updated without access to the corresponding SysConfig files, as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync. Link: https://lore.kernel.org/r/20260225132425.3096103-1-sparsh-kumar@ti.com 
Sparsh Kumar <sparsh-kumar@ti.com> says:

This series updates the Resource Management (RM) configuration files
for AM62 family devices to align with the TIFS v11.02.09 firmware.

Background
----------
With the latest TIFS firmware (v11.02.09), an additional virtual
interrupt and event is reserved for MCU cores to DM usage on am62x,
am62ax, and am62px devices. This series brings the rm-cfg and
tifs-rm-cfg files in sync with these firmware changes across both
TI reference boards and vendor boards.

These changes are backward compatible with older TIFS firmware versions.

Additionally, the am62x platform was originally introduced without a
tifs-rm-cfg.yaml file, unlike other platforms in the AM62 family.
This series addresses that gap and enables tifs-rm-cfg in binman for
am625-sk and am62p-sk platforms.

Changes
-------
TI reference boards (patches 1-4):
  - Update rm-cfg.yaml for am62x, am62ax, am62px
  - Sync am62px tifs-rm-cfg.yaml with TIFS firmware template
  - Add missing tifs-rm-cfg.yaml for am62x
  - Enable tifs-rm-cfg in binman for am625-sk and am62p-sk

Vendor boards (patches 5-9):
  - beagleplay (am62x-based)
  - phytec phycore_am62x
  - toradex verdin-am62
  - phytec phycore_am62ax
  - toradex verdin-am62p

with the required interrupt reservation. The tifs-rm-cfg.yaml files
cannot be updated without access to the corresponding SysConfig files,
as both rm-cfg.yaml and tifs-rm-cfg.yaml must remain in sync.

Link: https://lore.kernel.org/r/20260225132425.3096103-1-sparsh-kumar@ti.com
board: toradex: verdin-am62p: rm-cfg: Update rm-cfg to reflect new resource reservation 2026-03-13T20:57:21+00:00 Sparsh Kumar sparsh-kumar@ti.com 2026-02-25T13:24:25+00:00 a66704e9a18ba3a290a95ab22d87ecc3e2b62f56 With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62px devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com> 
With the latest v11.02.09 TIFS firmware, an additional
virtual interrupt and event is reserved for MCU cores
to DM usage on am62px devices.

Update the rm-cfg to reflect this new reservation.

Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com>
toradex: verdin-am62: rm-cfg: Update rm-cfg to reflect new resource reservation 2026-03-13T20:57:21+00:00 Sparsh Kumar sparsh-kumar@ti.com 2026-02-25T13:24:23+00:00 64ebab10b5eaebce34d455201581216fb72a8ecc With the latest v11.02.09 TIFS firmware, an additional virtual interrupt and event is reserved for MCU cores to DM usage on am62x devices. Update the rm-cfg to reflect this new reservation. Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com> 
With the latest v11.02.09 TIFS firmware, an additional
virtual interrupt and event is reserved for MCU cores
to DM usage on am62x devices.

Update the rm-cfg to reflect this new reservation.

Signed-off-by: Sparsh Kumar <sparsh-kumar@ti.com>