u-boot-toradex.git/drivers/ddr/altera/Kconfig, branch master U-Boot bootloader for Apalis and Colibri modules Replace TARGET namespace and cleanup properly 2026-02-14T17:06:46+00:00 Tien Fong Chee tien.fong.chee@altera.com 2026-02-13T12:27:23+00:00 62f7a94602094617ac384839ed695c2906893a88 TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune <briansune@gmail.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> # Conflicts: # drivers/ddr/altera/Makefile 
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.

Signed-off-by: Brian Sune <briansune@gmail.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

# Conflicts:
#	drivers/ddr/altera/Makefile
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 2021-03-08T02:59:10+00:00 Siew Chin Lim elly.siew.chin.lim@intel.com 2021-03-01T12:04:10+00:00 9a5bbdfd1a952901bda567d7d56225374ef883bc Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> 
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
ddr: altera: agilex: Add SDRAM driver for Agilex 2020-01-07T13:38:33+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-11-27T07:55:27+00:00 6a48c34c250e41765951586d3389c0df69b2dbe1 Add SDRAM driver for Agilex SoC. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 
Add SDRAM driver for Agilex SoC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arm: socfpga: Move Stratix 10 SDRAM driver to DM 2019-05-06T10:44:17+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-05-06T01:56:01+00:00 6bf238a46192bf9164da4548178d657dde4e1c96 Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 
Convert Stratix 10 SDRAM driver to device model.

Get rid of call to socfpga_per_reset() and use reset
framework.

SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.

Move sdram_s10.h from arch to driver/ddr/altera directory.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
ddr: altera: Compile ALTERA SDRAM in SPL only 2019-05-06T10:44:17+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-05-06T01:55:59+00:00 5918afda9d43106dd540c04bb05b7718e5f82171 Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 
Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arm: socfpga: move gen5 SDR driver to DM 2019-04-17T20:20:16+00:00 Simon Goldschmidt simon.k.r.goldschmidt@gmail.com 2019-04-16T20:04:39+00:00 29873c74f367474faafd16376e2a9f404172fbdd To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.

This gets us rid of one ad-hoc call to socfpga_per_reset().

The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.

SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
configs: Add DDR Kconfig support for Arria 10 2018-05-18T08:30:47+00:00 Tien Fong Chee tien.fong.chee@intel.com 2017-12-05T07:58:03+00:00 901af3e903c09c7681197a03367d82286f9f6e3f This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org> 
This patch enables DDR Kconfig support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig 2017-04-14T12:06:57+00:00 Ley Foon Tan ley.foon.tan@intel.com 2017-04-05T09:32:51+00:00 707cd012e2e1dbed7150f7908727abb7bdc4c1a7 Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> 
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>