u-boot-toradex.git/drivers, branch master

net: phy: mscc: add support for the VSC8572

2026-05-06T09:07:22+00:00

This is similar to the VSC8574 according to the Linux commit that adds
support for it [1].

This was tested on an HX1000 board with SGMII (PIC64-HX SoC which has a
GEM MAC).

[1]: https://lore.kernel.org/all/dfabe39a52efcd2cfff9358f271b8673143503b8.1480497966.git.neill.whillans@codethink.co.uk/

Signed-off-by: Charles Perry 
Reviewed-by: Manikandan Muralidharan

net: macb: add gigabit implementation for fixed-link

2026-05-06T09:07:22+00:00

A fixed gigabit link on a non-gigabit controller is only rejected
during PHY init (even though there is no PHY to init), because, on
device-tree parsing, the controller is not probed, and it is still
unknown whether it is gigabit-capable.

This code was only tested on emulator with a full-duplex RGMII
interface, but is expected to work in GMII or half-duplex as well.

Signed-off-by: Christian DREHER

net: macb: do not set user_io when it does not exist

2026-05-06T09:07:22+00:00

Cadence Ethernet MAC has a feature named user_io, which provides
some input and some output signals for arbitrary purpose in the SoC.
From the driver code, I understand that, on Atmel SoC, it is used to
drive the PHY mode.

At least on Cadence IP7014 r1p12, this feature is optional, and I am
working on a SoC that does not instantiate it. The presence of this
feature is advertised in DCFG1, this patch merely disables the access
to the user_io register based on this information.

I did not apply this change to the non-gigabit capable versions of
the IP, as I do not have documentation for them, and a new non-gigabit
instance is unlikely to appear. I prefer avoiding regressions on old
systems.

Signed-off-by: Christian DREHER

net: macb: use SA1 for MAC filtering on GEM

2026-05-06T09:07:22+00:00

The MACB uses specific address registers (SA Top and Bottom) to
filter source or destination MAC addresses.
On the Gigabit Ethernet version, SA1B is @0x88.
On the non-GEM version, SA1B is @0x98.

Before this commit, the code was always writing 0x98. By chance,
on GEM, this is the address of SA3B, allowing the driver to work
anyway.

The motivation for this change is to be able to use the driver on
an instance of the GEM with less than 4 SA registers.

Signed-off-by: Christian DREHER

net: macb: include arch/clk.h only when necessary

2026-05-06T09:07:22+00:00

It does not exist in my setup (an on-going arm64 SoC), and removing
it does not cause any missing declaration, but some code called when
CONFIG_CLK is missing calls get_macb_pclk_rate, which is only defined
in arch/arm/mach-at91/include/mach/clk.h

Signed-off-by: Christian DREHER

net: phy: adin: add support for the ADIN1200 phy

2026-05-06T09:07:22+00:00

The ADIN1200 chip is register compatible with the ADIN1300, but only
supports 10/100 Mbit.

Signed-off-by: Rasmus Villemoes

net: phy: airoha: air_en8811: use standard rx-polarity/tx-polarity properties

2026-05-06T09:07:22+00:00

Replace the proprietary airoha,pnswap-rx / airoha,pnswap-tx boolean
device tree properties with the standard rx-polarity and tx-polarity
properties defined in phy-common-props.yaml.

Backward compatibility is maintained by reading the legacy boolean
properties first and passing them as the default_pol argument to
phy_get_rx/tx_polarity(). If the standard properties are absent the
legacy values are used transparently, so existing device trees remain
functional without modification.

Link: https://git.kernel.org/linus/66d8a334b57e64e43810623b3d88f0ce9745270b
Signed-off-by: Lucien.Jheng

phy: add common PHY properties support

2026-05-06T09:07:22+00:00

Add a new PHY_COMMON_PROPS library that provides helper functions for
PHY drivers to read standardized polarity properties from the device
tree node:

  - phy_get_rx_polarity() / phy_get_tx_polarity()
  - phy_get_manual_rx_polarity() / phy_get_manual_tx_polarity()

The dt-bindings/phy/phy.h header with PHY_POL_NORMAL, PHY_POL_INVERT,
and PHY_POL_AUTO constants is provided via dts/upstream/include, which
is already in the build include path.

Ported from Merge tag 'phy-for-7.0':
  git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Link: https://git.kernel.org/linus/e7556b59ba65179612bce3fa56bb53d1b4fb20db
Signed-off-by: Lucien.Jheng

net: cpsw: Support new cpsw-switch DT bindings

2026-05-06T09:07:22+00:00

Upstream devicetrees use a newer DT binding using cpsw-switch
compatibles. The bindings are a bit different, so two functions are
introduced to capture the differences, cpsw_eth_of_to_plat_switch() and
cpsw_eth_of_to_plat_legacy().

Signed-off-by: Markus Schneider-Pargmann (TI)

net: cpsw: Use driver data for phy_sel

2026-05-06T09:07:22+00:00

Use driver data to pass the correct gmii_sel function. This way new
compatibles don't need manual compatible matching as is done in
cpsw_phy_sel().

Signed-off-by: Markus Schneider-Pargmann (TI)