diff options
| author | briansune <briansune@gmail.com> | 2025-09-24 02:12:54 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-10-07 17:49:15 -0600 |
| commit | 92dcb3ad5d98f494b2448a7345e1cb7eefa50278 (patch) | |
| tree | 238b28fd64c08a61aeb66c3017e64d075e0a8099 | |
| parent | e560735558e313be8e883f9efcf729997df8b30e (diff) | |
This adds a new U-Boot command 'c5_pl330_dma' for Cyclone V SoCDK
boards. It provides access to the Reset Manager's Per2ModRst register
to release the reset for ARM PrimeCell PL330 DMA channels. This allows
software to initialize and use the PL330 DMA controller properly after
reset.
Signed-off-by: Brian Sune <briansune@gmail.com>
[trini: Minor style fixes]
Signed-off-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | cmd/Kconfig | 8 | ||||
| -rw-r--r-- | cmd/Makefile | 1 | ||||
| -rw-r--r-- | cmd/c5_pl330_dma.c | 49 |
3 files changed, 58 insertions, 0 deletions
diff --git a/cmd/Kconfig b/cmd/Kconfig index 29de857ba7c..e0101ca6f82 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1791,6 +1791,14 @@ endmenu menu "Shell scripting commands" + +config CMD_C5_PL330_DMA + bool "Release Reset DMA Channels for PL330 Handshake" + depends on TARGET_SOCFPGA_CYCLONE5_SOCDK + help + Provides access to Reset Manager Per2ModRst. Enables DMA + channels for ARM PrimeCell PL330 via reset release. + config CMD_CAT bool "cat" help diff --git a/cmd/Makefile b/cmd/Makefile index 36e79cc3c28..25479907797 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_CMD_BOOTZ) += bootz.o obj-$(CONFIG_CMD_BOOTI) += booti.o obj-$(CONFIG_CMD_BTRFS) += btrfs.o obj-$(CONFIG_CMD_BUTTON) += button.o +obj-$(CONFIG_CMD_C5_PL330_DMA) += c5_pl330_dma.o obj-$(CONFIG_CMD_CAT) += cat.o obj-$(CONFIG_CMD_CACHE) += cache.o obj-$(CONFIG_CMD_CBFS) += cbfs.o diff --git a/cmd/c5_pl330_dma.c b/cmd/c5_pl330_dma.c new file mode 100644 index 00000000000..75e8c9b0d92 --- /dev/null +++ b/cmd/c5_pl330_dma.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Brian Sune <briansune@gmail.com> + */ + +#include <vsprintf.h> +#include <command.h> +#include <asm/io.h> + +#include <asm/arch/base_addr_ac5.h> + +#define RSTMGR_PERMODRST 0x18 /* PERMODRST register offset */ + +static int do_dmareset(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u8 val; + int i, ch; + + if (argc < 2) { + printf("Usage: dmareset <channel 0-7> [<channel 0-7> ...]\n"); + return CMD_RET_USAGE; + } + + /* Read current register value */ + val = readb(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_PERMODRST); + + /* Iterate over all channels given as arguments */ + for (i = 1; i < argc; i++) { + ch = simple_strtoul(argv[i], NULL, 0); + if (ch < 0 || ch > 7) { + printf("Error: channel must be 0-7\n"); + return CMD_RET_USAGE; + } + val &= ~(1 << ch); + printf("PL330 DMA channel %d reset released\n", ch); + } + + /* Write back */ + writeb(val, (SOCFPGA_RSTMGR_ADDRESS + RSTMGR_PERMODRST)); + + return 0; +} + +U_BOOT_CMD( + dmareset, 8, 0, do_dmareset, + "Release PL330 DMA channel reset(s) for SoCFPGA", + "dmareset <channel 0-7> [<channel 0-7> ...] - release reset for one or more DMA channels" +); |