diff options
| author | Sekhar Nori <nsekhar@ti.com> | 2009-03-23 12:50:51 +0530 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-09-09 14:03:22 -0400 |
| commit | 6a92c7e85e73f43f4153864895cd93f5e56d094e (patch) | |
| tree | 831697c49df209582fda4e51e39a214139dc1b2e | |
| parent | 7cdd11906cae61cbe3d01418ac132022c36925c4 (diff) | |
U-Boot: cleanup clock handling code
A side-effect of this is that it allows geting PLLM and PLLC clocks for PLL1
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| -rw-r--r-- | cpu/arm926ejs/da8xx/clock.c | 15 | ||||
| -rw-r--r-- | include/asm-arm/arch-da8xx/hardware.h | 39 |
2 files changed, 34 insertions, 20 deletions
diff --git a/cpu/arm926ejs/da8xx/clock.c b/cpu/arm926ejs/da8xx/clock.c index ff8e36ce5a..a98d016e9b 100644 --- a/cpu/arm926ejs/da8xx/clock.c +++ b/cpu/arm926ejs/da8xx/clock.c @@ -34,17 +34,20 @@ int clk_get(unsigned int id) int post_div; volatile unsigned int pll_base; - if ((id >> 8) == 1) + if(id == AUXCLK) + goto out; + + if ((id >> 16) == 1) pll_base = DAVINCI_PLL_CNTRL1_BASE; else pll_base = DAVINCI_PLL_CNTRL0_BASE; + id &= 0xFF; + pre_div = (REG(pll_base + PLL_PREDIV) & 0xff) + 1; pllm = REG(pll_base + PLL_PLLM) + 1; post_div = (REG(pll_base + PLL_POSTDIV) & 0xff) + 1; - if(id == DAVINCI_AUXCLK_CLKID) - goto out; /* Lets keep this simple. Combining operations can result in * unexpected approximations @@ -52,15 +55,15 @@ int clk_get(unsigned int id) pll_out /= pre_div; pll_out *= pllm; - if(id == DAVINCI_PLLM_CLKID) + if(id == PLLM) goto out; pll_out /= post_div; - if(id == DAVINCI_PLLC_CLKID) + if(id == PLLC) goto out; - pll_out /= (REG(pll_base + sysdiv[(id & 0xff) - 1]) & 0xff) + 1; + pll_out /= (REG(pll_base + sysdiv[id - 1]) & 0xff) + 1; out: return pll_out; diff --git a/include/asm-arm/arch-da8xx/hardware.h b/include/asm-arm/arch-da8xx/hardware.h index 88ff8ee0a1..e8cb2c4640 100644 --- a/include/asm-arm/arch-da8xx/hardware.h +++ b/include/asm-arm/arch-da8xx/hardware.h @@ -74,15 +74,30 @@ #define DAVINCI_DDR_EMIF_DATA_BASE (0xc0000000) #define DAVINCI_INTC_BASE (0xfffee000) +/* software identifiers for clock ids */ +#define PLL0_SYSCLK2 (0x2) +#define PLL0_SYSCLK4 (0x4) +#define PLL0_SYSCLK6 (0x6) +#define PLL1_SYSCLK2 ((1 << 16) | 0x2) +#define ASYNC3 get_async3_src() + +/* special clocks */ +#define PLLM (0xFF + 1) +#define PLLC (0xFF + 2) +#define AUXCLK (0xFF + 3) + +#define PLL0_PLLM PLLM +#define PLL0_PLLC PLLC +#define PLL1_PLLM ((1 << 16) | PLLM) +#define PLL1_PLLC ((1 << 16) | PLLC) + /* Clock IDs */ -#define DAVINCI_PLLM_CLKID (0xFF + 0) -#define DAVINCI_PLLC_CLKID (0xFF + 1) -#define DAVINCI_AUXCLK_CLKID (0xFF + 2) -#define DAVINCI_MDIO_CLKID 0x0004 -#define DAVINCI_SPI0_CLKID 0x0002 -#define DAVINCI_UART0_CLKID 0x0002 -#define DAVINCI_UART2_CLKID ((cpu_is_da830()) ? 0x0002 : (clk_src() ? 0x0102 : 0x0002)) -#define DAVINCI_ARM_CLKID 0x0006 +#define DAVINCI_AUXCLK_CLKID AUXCLK +#define DAVINCI_MDIO_CLKID PLL0_SYSCLK4 +#define DAVINCI_SPI0_CLKID PLL0_SYSCLK2 +#define DAVINCI_UART0_CLKID PLL0_SYSCLK2 +#define DAVINCI_UART2_CLKID (cpu_is_da830() ? PLL0_SYSCLK2 : ASYNC3) +#define DAVINCI_ARM_CLKID PLL0_SYSCLK6 /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 @@ -213,13 +228,9 @@ static int cpu_is_da850(void) return ((part_no == 0xb7d1) ? 1 : 0); } -static int clk_src(void) +static inline int get_async3_src(void) { - unsigned int cfgchip3 = REG(CFGCHIP3); - - cfgchip3 &= 0x00000010; - - return (cfgchip3 ? 1 : 0); + return ((REG(CFGCHIP3) & 0x10) ? PLL1_SYSCLK2 : PLL0_SYSCLK2); } #endif |