diff options
| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-10-07 15:47:48 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:48 -0400 |
| commit | dc89a49f05650be605fb5bd134eedcf5224fc689 (patch) | |
| tree | 5e908335f643a8f77e8320e378ef2e5195b6082d | |
| parent | 8ff56326996a13dd0755fbcd4f02694a074f2722 (diff) | |
u-boot-2009.03-p2020rdb-RevA-DDR-fixes
Modified DDR Settings for P2020RDB REV-A Board.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
| -rw-r--r-- | include/configs/P10XX_20XX_RDB.h | 12 | ||||
| -rw-r--r-- | nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c | 20 |
2 files changed, 16 insertions, 16 deletions
diff --git a/include/configs/P10XX_20XX_RDB.h b/include/configs/P10XX_20XX_RDB.h index 8e2b6ea5b3..9481010366 100644 --- a/include/configs/P10XX_20XX_RDB.h +++ b/include/configs/P10XX_20XX_RDB.h @@ -126,18 +126,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 /* Enable, no interleaving */ #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_TIMING_3_REVA 0x00010000 +#define CONFIG_SYS_DDR_TIMING_3_REVA 0x00020000 #define CONFIG_SYS_DDR_TIMING_0_REVA 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1_REVA 0x4c47a432 -#define CONFIG_SYS_DDR_TIMING_2_REVA 0x04984cce +#define CONFIG_SYS_DDR_TIMING_1_REVA 0x4c47c432 +#define CONFIG_SYS_DDR_TIMING_2_REVA 0x0f9848ce #define CONFIG_SYS_DDR_TIMING_4_REVA 0x00000000 #define CONFIG_SYS_DDR_TIMING_5_REVA 0x00000000 +#define CONFIG_SYS_DDR_CLK_CTRL_REVA 0x02800000 #define CONFIG_SYS_DDR_MODE_1_REVA 0x00040642 #define CONFIG_SYS_DDR_MODE_2_REVA 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_REVA 0x08200100 -#define CONFIG_SYS_DDR_CLK_CTRL_REVA 0x03800000 -#define CONFIG_SYS_DDR_CONTROL_REVA 0x43000008 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2_REVA 0x24400010 +#define CONFIG_SYS_DDR_CONTROL_REVA 0x43000000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL2_REVA 0x24401000 #define CONFIG_SYS_DDR_TIMING_3_533_REVB 0x00020000 #define CONFIG_SYS_DDR_TIMING_0_533_REVB 0x00260802 diff --git a/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c b/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c index 12efea410e..7e078b4b17 100644 --- a/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c +++ b/nand_spl/board/freescale/p10xx_p20xx_rdb/nand_boot.c @@ -35,16 +35,16 @@ void initsdram(void) out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_REVA); + out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_REVA); + out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_REVA); + out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_REVA); + out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_REVA); + out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_REVA); + out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_REVA); out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2); + out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_REVA); + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2_REVA); #if defined(CONFIG_DDR_ECC) out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); @@ -54,7 +54,7 @@ void initsdram(void) asm("sync;isync"); udelay(200); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL_REVA); } void board_init_f_nand(void) |