diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2013-07-17 12:46:15 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-20 12:14:09 -0400 |
| commit | fdf86c202c17adfc6f6313dc35f685b1d22b8125 (patch) | |
| tree | 6da1ab7200f5bd65f793f01d4faf6192b12d6743 | |
| parent | 9a5dad239332537a5689131bbcc705c1f9c0cb41 (diff) | |
ddr cfg: DRAM_RESET needs 0x00020030
The old value of 0x000e0030 will cause ethernet
timeout issues on the sabrelite and possibly other
boards using the KSZ9021.
I have no explanation as to why.
But this is a correct change, the TRM will be updated
to show that 00b is the only valid setting for bits
19-18 of DRAM_RESET.
My thanks go to Liu Hui(Jason) for this information.
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| -rw-r--r-- | board/boundary/nitrogen6x/ddr-setup.cfg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg index c3158120a40..e5f8add7447 100644 --- a/board/boundary/nitrogen6x/ddr-setup.cfg +++ b/board/boundary/nitrogen6x/ddr-setup.cfg @@ -74,7 +74,7 @@ DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 -DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 |