NOR flash sync support

2 files changed, 105 insertions, 6 deletions

diff --git a/board/omap3/logic/logic.c b/board/omap3/logic/logic.c
index d703913c48..807f91b33f 100644
--- a/board/omap3/logic/logic.c
+++ b/board/omap3/logic/logic.c
@@ -97,6 +97,7 @@ int board_init(void)
 
 static void setup_net_chip(void);
 static void setup_isp1760_chip(void);
+static void fix_flash_sync(void);
 
 /*
  * Routine: misc_init_r
@@ -120,6 +121,7 @@ int misc_init_r(void)
 	/* Setup access to the isp1760 chip on CS6 */
 	setup_isp1760_chip();
 
+	/* Fix the flash sync */
 	twl4030_power_init();
 	twl4030_led_init();
 
@@ -136,8 +138,7 @@ int misc_init_r(void)
 
 	gd->bd->bi_arch_number = logic_identify();
 
-	/* Switch to Hardware ECC mode */
-	omap_nand_switch_ecc(1);
+	fix_flash_sync();
 
 	dieid_num_r();
 
@@ -222,14 +223,12 @@ static void setup_net_chip(void)
 #define LOGIC_ISP1760_GPMC_CONFIG7  0x00000f5c
 
 /*
- * Routine: setup_net_chip
+ * Routine: setup_isp1760_chip
  * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
+ *		ISP1760 USB hardware.
  */
 static void setup_isp1760_chip(void)
 {
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
 	/* Configure GPMC registers */
 	writel(LOGIC_ISP1760_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
 	writel(LOGIC_ISP1760_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
@@ -240,6 +239,104 @@ static void setup_isp1760_chip(void)
 	writel(LOGIC_ISP1760_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
 }
 
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG1	0x00001211
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG2	0x00080901
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG3	0x00020201
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG4	0x08010901
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG5	0x0008090a
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG6	0x08030200
+#define LOGIC_STNOR_ASYNC_GPMC_CONFIG7	0x00000c50
+
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG1	0x68411213
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG2	0x000C1502
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG3	0x00040402
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG4	0x0B051505
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG5	0x020E0C15
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG6	0x0B0603C3
+#define LOGIC_STNOR_SYNC_GPMC_CONFIG7	0x00000c50
+
+#define LOGIC_FLASH_BASE 0x10000000
+
+/* These are bit definitions for the RCR register of the NOR flash       */
+/* 28FxxxP30 device.  This register sets the bus configration for reads. */
+/* settings, located on address pins A[15:0].                            */
+#define FLASH_28FxxxP30_RCR_RM    0x8000
+#define FLASH_28FxxxP30_RCR_R     0x4000
+#define FLASH_28FxxxP30_RCR_LC(x) ((x & 0x7) << 11)
+#define FLASH_28FxxxP30_RCR_WP    0x0400
+#define FLASH_28FxxxP30_RCR_DH    0x0200
+#define FLASH_28FxxxP30_RCR_WD    0x0100
+#define FLASH_28FxxxP30_RCR_BS    0x0080
+#define FLASH_28FxxxP30_RCR_CE    0x0040
+#define FLASH_28FxxxP30_RCR_BW    0x0008
+#define FLASH_28FxxxP30_RCR_BL(x) ((x & 0x7) << 0)
+#define FLASH_28FxxxP30_BL_4      0x1
+#define FLASH_28FxxxP30_BL_8      0x2
+#define FLASH_28FxxxP30_BL_16     0x3
+#define FLASH_28FxxxP30_BL_CONT   0x7
+
+/*
+ * Routine: fix_flash_sync
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		NOR flash (and place in sync mode if not done).
+ */
+static void fix_flash_sync(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int arch_number;
+	u16 rcrval;
+
+	/* Check the arch_number - Torpedo doesn't have NOR flash */
+	arch_number = gd->bd->bi_arch_number;
+	if (arch_number == MACH_TYPE_OMAP3_TORPEDO)
+		return;
+
+	/* Check CS2 config, if its already in sync, then return */
+	if (!(readl(&gpmc_cfg->cs[2].config1) & TYPE_READTYPE)) {
+		puts("NOR: initialize in sync mode\n");
+
+		/* clear WAIT1 polarity */
+		writel(readl(&gpmc_cfg->config) & ~0x200, &gpmc_cfg->config);
+
+		/* clear GPMC_TIMEOUT */
+		writel(0x0, &gpmc_cfg->timeout_control);
+
+		/* Configure GPMC registers for async */
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG1, &gpmc_cfg->cs[2].config1);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG2, &gpmc_cfg->cs[2].config2);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG3, &gpmc_cfg->cs[2].config3);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG4, &gpmc_cfg->cs[2].config4);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG5, &gpmc_cfg->cs[2].config5);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG6, &gpmc_cfg->cs[2].config6);
+		writel(LOGIC_STNOR_ASYNC_GPMC_CONFIG7, &gpmc_cfg->cs[2].config7);
+
+		/* 1st NOR cycle, send read config register setup 0x60 */
+		*(volatile u16 *)LOGIC_FLASH_BASE = 0x0060;
+
+		/* 2nd NOR cycle, send 0x03 to latch in read
+		 * configuration register setttings, located on A[15:0] */
+		rcrval = FLASH_28FxxxP30_RCR_LC(4) | FLASH_28FxxxP30_RCR_WP |
+		  FLASH_28FxxxP30_RCR_BS | FLASH_28FxxxP30_RCR_CE |
+		  FLASH_28FxxxP30_RCR_BW | FLASH_28FxxxP30_RCR_BL(FLASH_28FxxxP30_BL_4);
+		*(volatile u16 *)(LOGIC_FLASH_BASE | (rcrval << 1)) = 0x0003;
+
+		/* Give a chance for accesses to finish... */
+		sdelay(2000);
+
+		/* Third, set GPMC for sync. */
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG1, &gpmc_cfg->cs[2].config1);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG2, &gpmc_cfg->cs[2].config2);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG3, &gpmc_cfg->cs[2].config3);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG4, &gpmc_cfg->cs[2].config4);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG5, &gpmc_cfg->cs[2].config5);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG6, &gpmc_cfg->cs[2].config6);
+		writel(LOGIC_STNOR_SYNC_GPMC_CONFIG7, &gpmc_cfg->cs[2].config7);
+		/* And lastly, set the WAIT1 polarity high */
+		writel(readl(&gpmc_cfg->config) | 0x200, &gpmc_cfg->config);
+	} else
+		puts ("NOR: Already initialized in sync mode\n");
+}
+
 
 int board_eth_init(bd_t *bis)
 {
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h
index 8df6a83720..937683f32e 100644
--- a/include/asm-arm/arch-omap3/omap3.h
+++ b/include/asm-arm/arch-omap3/omap3.h
@@ -179,6 +179,8 @@ struct gpio {
 
 #define CPU_3XX_ID_SHIFT	28
 
+#define TYPE_READTYPE		0x20000000  // Readtype, 1==sync in gpmc
+
 #define WIDTH_8BIT		0x0000
 #define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */