diff options
| author | Sandeep Gopalpet <sandeep.kumar@freescale.com> | 2010-03-11 15:43:32 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:25 -0500 |
| commit | 1970f67b8b1ae3bfd1ff0cdfa6945da2037d8ca9 (patch) | |
| tree | 64053f64efc423f848f1a1862a777e15ca56adbd | |
| parent | f51d2ef6970d1fe1a09b28d7be8755036d36fb80 (diff) | |
85xx/p1_p2_rdb: p1020: DDR changes
Signed-off-by: Maneesh Gupta <maneesh.gupta@freescale.com>
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 12 | ||||
| -rw-r--r-- | nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 9 |
2 files changed, 18 insertions, 3 deletions
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index cc09046fba..3938b45c91 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -245,9 +245,17 @@ phys_size_t fixed_sdram (void) phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; + struct cpu_type *cpu; #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_FSL_BOOT_DDR) - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + cpu = gd->cpu; + + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) + return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 2; + else + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif dram_size = fixed_sdram(); set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c index 1dabb3cf0e..35e58a3078 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -54,6 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_DDR_MODE_1_667 0x00040852 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 +#define SDRAM_CFG_32_BE 0x00080000 #define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j < 10000; j++); } @@ -81,7 +82,13 @@ void initsdram(void) out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); + +#if defined(CONFIG_P2020) || defined(CONFIG_P2010) out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); +#elif defined(CONFIG_P1020) || defined(CONFIG_P1011) + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); +#endif + out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); asm("sync;isync"); |