diff options
| author | Sandeep Gopalpet <sandeep.kumar@freescale.com> | 2010-03-17 19:29:06 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:25 -0500 |
| commit | 817fca2e73267b9451cc514b757a50c80d43c000 (patch) | |
| tree | 48e986355f6ea4a6f1f84fa88e1f4263b695c6ad | |
| parent | 4d839f85b0f13497e07309b4fa34d162a946418a (diff) | |
Set HID1[mbdd] bit for optimal eieio
This patch checks the version number and revision number
from the pvr register and sets the HID1[mbdd] bit accordingly.
HID1[mbdd] is found on the new revisions of the e500 cores
which will optimize eieio instruction.
By setting this bit, a 10% improvement is seen in
applications like IP forwarding.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/release.S | 9 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 9 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 1 |
3 files changed, 17 insertions, 2 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 433ff02544..a0010b8636 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2010 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -57,6 +57,13 @@ __secondary_start_page: #ifndef CONFIG_E500MC li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r0,PVR + andi. r0,r0,0xff + cmpwi r0,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r3, r3, HID1_MBDD@l +1: mtspr SPRN_HID1,r3 #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 6a865283d4..88fbfde92a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor. + * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -174,6 +174,13 @@ _start_e500: #ifndef CONFIG_E500MC li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mfspr r3,PVR + andi. r3,r3, 0xff + cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */ + blt 1f + /* Set MBDD bit also */ + ori r0, r0, HID1_MBDD@l +1: mtspr HID1,r0 #endif diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f61778f864..764178bcb3 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |