diff options
| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2009-10-23 17:40:34 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:24 -0500 |
| commit | 81bafe293fcea0bdf1f86ade540d6e19a5b378be (patch) | |
| tree | 409c2fe0b5d98f5c311c90aa7d6a8afe867337c6 | |
| parent | ac580e091467a589b13ada4c2e8427099ecc9aa8 (diff) | |
Workaround for AHB2MAG IRQ Bypass
This is a workaround for the hardware bug found on the P2020 Rev 1.0.
The DCR[DMA__AHB2MAG_IRQ_BYPASS]is not set automatically upon SoC reset.
This patch sets the bit.
Signed-off-by: Vishnu Suresh <Vishnu@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 18f92d0c02..1cf17d650f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -369,7 +369,7 @@ static int esdhc_init(struct mmc *mmc) int timeout = 1000; /* Enable cache snooping */ - out_be32(®s->scr, 0x00000040); + setbits_be32(®s->scr, 0x00000040); out_be32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); @@ -424,6 +424,10 @@ static int esdhc_initialize(bd_t *bis) mmc_register(mmc); +#ifdef CONFIG_P2020 + /* Enable AHB2MAG IRQ Bypass */ + setbits_be32(®s->scr, 0x00000020); +#endif return 0; } |