diff options
| author | Dipen Dudhat <dipen.dudhat@freescale.com> | 2010-03-18 17:45:14 +0530 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-11-10 14:52:25 -0500 |
| commit | 921a50f144c307dd3ab3e9343de8c5bfd22bb4c8 (patch) | |
| tree | d1833bf320609b84c57ecac78442178ece25ec50 | |
| parent | 3d0bc92072df6641d9491858653c2d864421d202 (diff) | |
Assign Initial clock speed for eSDHC controller
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, the field 'clock' is assigned the initial clock speed 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d3ffb2fef7..ed14b2f42b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -374,6 +374,7 @@ static int esdhc_init(struct mmc *mmc) out_be32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ + mmc->clock = 400000; set_sysctl(mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ |