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authorPaul Burton <paul.burton@imgtec.com>2016-05-27 14:28:04 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-05-31 09:44:24 +0200
commitace3be4f15875d74344336b9754c14274f940969 (patch)
tree462b0bcc538f617028dbf06221cdeb26d2ce0c01
parent83b0face8c710f719445f3c282c2ca6fad326bd7 (diff)
MIPS: Move cache sizes to Kconfig
Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat
-rw-r--r--arch/mips/Kconfig28
-rw-r--r--arch/mips/lib/cache.c2
-rw-r--r--arch/mips/lib/cache_init.S6
-rw-r--r--board/dbau1x00/Kconfig9
-rw-r--r--board/micronas/vct/Kconfig9
-rw-r--r--board/pb1x00/Kconfig9
-rw-r--r--board/qca/ap121/Kconfig9
-rw-r--r--board/qca/ap143/Kconfig9
-rw-r--r--board/qemu-mips/Kconfig9
-rw-r--r--board/tplink/wdr4300/Kconfig9
-rw-r--r--include/configs/ap121.h5
-rw-r--r--include/configs/ap143.h5
-rw-r--r--include/configs/dbau1x00.h7
-rw-r--r--include/configs/pb1x00.h6
-rw-r--r--include/configs/qemu-mips.h7
-rw-r--r--include/configs/qemu-mips64.h7
-rw-r--r--include/configs/tplink_wdr4300.h5
-rw-r--r--include/configs/vct.h7
18 files changed, 95 insertions, 53 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a9294527df7..a79224e525e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -246,6 +246,34 @@ config SWAP_IO_SPACE
config SYS_MIPS_CACHE_INIT_RAM_LOAD
bool
+config SYS_DCACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+ int
+ default 0
+ help
+ The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+ int
+ default 0
+ help
+ The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+ def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+ SYS_CACHELINE_SIZE = 0
+ help
+ Select this (or let it be auto-selected by not defining any cache
+ sizes) in order to allow U-Boot to automatically detect the sizes
+ of caches at runtime. This has a small cost in code size & runtime
+ so if you know the cache configuration for your system at compile
+ time it would be beneficial to configure it.
+
config MIPS_L1_CACHE_SHIFT_4
bool
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005b679..fbaafee8cde 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,7 +9,7 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
static inline unsigned long icache_line_size(void)
{
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3af525..4bb9a17e749 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,14 +99,14 @@
*
*/
LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t2, CONFIG_SYS_ICACHE_SIZE
li t8, CONFIG_SYS_CACHELINE_SIZE
#else
l1_info t2, t8, MIPS_CONF1_IA_SHF
#endif
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
li t3, CONFIG_SYS_DCACHE_SIZE
li t9, CONFIG_SYS_CACHELINE_SIZE
#else
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
li v0, CONFIG_SYS_ICACHE_SIZE
#else
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 342ec59cb73..1715a289755 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0xbfc00000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
menu "dbau1x00 board options"
choice
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 535a77b2a32..5bb6f03f30f 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x87000000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
menu "vct board options"
choice
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 236a4108bfc..27b2ef000b0 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x83800000
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index c3ecc8f62ff..f28ea1cd44f 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x9f000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 5ea5d6fbb02..ff02236d5d8 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0x9f000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 3de1f44a3da..66957e7a57a 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -11,4 +11,13 @@ config SYS_TEXT_BASE
default 0xbfc00000 if 32BIT
default 0xffffffffbfc00000 if 64BIT
+config SYS_DCACHE_SIZE
+ default 16384
+
+config SYS_ICACHE_SIZE
+ default 16384
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 65785bdb9c7..ded7f9b1798 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
config SYS_TEXT_BASE
default 0xa1000000
+config SYS_DCACHE_SIZE
+ default 32768
+
+config SYS_ICACHE_SIZE
+ default 65536
+
+config SYS_CACHELINE_SIZE
+ default 32
+
endif
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 6f69f31503c..f069d501302 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index f907c02af92..e45f743936d 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 325
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 68d9e36b19c..68ff02509b5 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -202,11 +202,4 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif /* CONFIG_DBAU1550 */
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 869768add05..b907419a598 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -144,12 +144,6 @@
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
#endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* BOOTP options
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 246ee0173a7..f58fc4c3779 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -132,11 +132,4 @@
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 60a3a71fbdc..2190d162007 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -132,11 +132,4 @@
#define CONFIG_LZMA
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#endif /* __CONFIG_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 09a69fec09d..6273711b1d0 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -15,11 +15,6 @@
#define CONFIG_SYS_MHZ 280
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE 0x8000
-#define CONFIG_SYS_ICACHE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x40000
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 68eb0893948..cc5e3546b08 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -204,13 +204,6 @@
#endif /* CONFIG_VCT_ONENAND */
/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
* I2C/EEPROM
*/
#define CONFIG_SYS_I2C
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-30 19:46:31 +0000