[Blackfin][PATCH] code cleanup

19 files changed, 518 insertions, 551 deletions

diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
index 677668e07b7..8f51eb2f955 100644
--- a/board/bf533-ezkit/Makefile
+++ b/board/bf533-ezkit/Makefile
@@ -1,9 +1,9 @@
 #
 # U-boot - Makefile
 #
-# Copyright (c) 2005-2007 Analog Device Inc.
+# Copyright (c) 2007 Analog Device Inc.
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S
index 4e16d9f7af8..9742e0297c0 100644
--- a/board/bf533-ezkit/u-boot.lds.S
+++ b/board/bf533-ezkit/u-boot.lds.S
@@ -150,4 +150,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
index 1efb851e709..217e5f00fdc 100644
--- a/board/bf533-stamp/Makefile
+++ b/board/bf533-stamp/Makefile
@@ -1,9 +1,9 @@
 #
 # U-boot - Makefile
 #
-# Copyright (c) 2005-2007 Analog Device Inc.
+# Copyright (c) 2007 Analog Device Inc.
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S
index 48d55fab1ed..03ef72b6090 100644
--- a/board/bf533-stamp/u-boot.lds.S
+++ b/board/bf533-stamp/u-boot.lds.S
@@ -150,4 +150,3 @@ SECTIONS
   _end = . ;
   PROVIDE (end = .);
 }
-
diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
index 82fcd576a98..0a04f3e8cef 100644
--- a/cpu/bf533/bf533_serial.h
+++ b/cpu/bf533/bf533_serial.h
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2005 blackfin.uclinux.org
  *
- * This file is based on 
+ * This file is based on
  * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
  * Copyright (C) 2003	Bas Vermeulen <bas@buyways.nl>
  * 			BuyWays B.V. (www.buyways.nl)
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index d2b34a9a37a..5dcc24fd52f 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -68,7 +68,7 @@ ENTRY(_invalidate_entire_icache)
 	(R7:5) =[SP++];
 	RTS;
 
-/* 
+/*
  * Invalidate the Entire Data cache by
  * clearing DMC[1:0] bits
  */
@@ -80,7 +80,7 @@ ENTRY(_dcache_invalidate)
 	P0.H = (DMEM_CONTROL >> 16);
 	R7 =[P0];
 
-/* 
+/*
  * Clear the DMC[1:0] bits, All valid bits in the data
  * cache are set to the invalid state
  */
@@ -118,7 +118,7 @@ ENTRY(_blackfin_dcache_invalidate_range)
 	CC = P0 < P1(iu);
 	IF CC JUMP 1b(bp);
 
-/* 
+/*
  * If the data crosses a cache line, then we'll be pointing to
  * the last cache line, but won't have flushed/invalidated it yet, so do
  * one more.
diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S
index 8010f72772e..58fe4c84b44 100644
--- a/cpu/bf533/flush.S
+++ b/cpu/bf533/flush.S
@@ -95,7 +95,7 @@ ENTRY(_icplb_flush)
 	 * R0 = Page start
 	 * R1 = Page length (actually, offset into size/prefix tables)
 	 * R3 = sub-bank deposit values
-  	 *
+	 *
 	 * The cache has 2 Ways, and 64 sets, so we iterate through
 	 * the sets, accessing the tag for each Way, for our Bank and
 	 * sub-bank, looking for dirty, valid tags that match our
@@ -142,7 +142,7 @@ ifs0:	R6 = R5 << 5;		/* Combine set*/
 	IF !CC JUMP ifskip;	/* Skip it if it doesn't match.*/
 
 	/* Tag address matches against page, so this is an entry
-	 * we must flush. 
+	 * we must flush.
 	 */
 
 	R7 >>= 10;		/* Mask off the non-address bits*/
@@ -185,7 +185,7 @@ ieall: NOP;
 	SSYNC;
 	JUMP ifinished;
 
-/* This is an external function being called by the user 
+/* This is an external function being called by the user
  * application through __flush_cache_all. Currently this function
  * serves the purpose of flushing all the pending writes in
  * in the data cache.
@@ -222,7 +222,7 @@ skip:	R6 += -1;
 
 /* This is an internal function to flush all pending
  * writes in the cache associated with a particular DCPLB.
- * 
+ *
  * R0 -  page's start address
  * R1 -  CPLB's data field.
  */
@@ -260,7 +260,7 @@ ENTRY(_dcplb_flush)
 	/* The page could be mapped into Bank A or Bank B, depending
 	 * on (a) whether both banks are configured as cache, and
 	 * (b) on whether address bit A[x] is set. x is determined
-	 * by DCBS in DMEM_CONTROL		
+	 * by DCBS in DMEM_CONTROL
 	 */
 	
 	R2 = 0;			/* Default to Bank A (Bank B would be 1)*/
diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S
index d92c877f593..1aae9e30f96 100644
--- a/cpu/bf533/init_sdram.S
+++ b/cpu/bf533/init_sdram.S
@@ -28,17 +28,17 @@ init_sdram:
 	[--SP] = (R7:0);
 	[--SP] = (P5:0);
 
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) 
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
 	p0.h = hi(SPI_BAUD);
 	p0.l = lo(SPI_BAUD);
 	r0.l = CONFIG_SPI_BAUD;
 	w[p0] = r0.l;
-    SSYNC;
+	SSYNC;
 #endif
 
 	/*
-         * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
-         */
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
 	p0.h = hi(PLL_LOCKCNT);
 	p0.l = lo(PLL_LOCKCNT);
 	r0 = 0x300(Z);
@@ -46,43 +46,43 @@ init_sdram:
 	ssync;
 
 	/*
-         * Put SDRAM in self-refresh, incase anything is running
-         */
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL with the value that we calculate in R0
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        r0 = CONFIG_VCO_MULT & 63;      /* Load the VCO multiplier         */
-        r0 = r0 << 9;                   /* Shift it over,                  */
-        r1 = CONFIG_CLKIN_HALF;        /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = CONFIG_PLL_BYPASS;         /* Bypass the PLL?                 */
-        r1 = r1 << 8;                   /* Shift it over                   */
-        r0 = r1 | r0;                   /* add them all together           */
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);             /* Load the address                */
-        cli r2;                         /* Disable interrupts              */
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier         */
+	r0 = r0 << 9;			/* Shift it over,                  */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL?                 */
+	r1 = r1 << 8;			/* Shift it over                   */
+	r0 = r1 | r0;			/* add them all together           */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address                */
+	cli r2;				/* Disable interrupts              */
 	ssync;
-        w[p0] = r0.l;                   /* Set the value                   */
-        idle;                           /* Wait for the PLL to stablize    */
-        sti r2;                         /* Enable interrupts               */
+	w[p0] = r0.l;			/* Set the value                   */
+	idle;				/* Wait for the PLL to stablize    */
+	sti r2;				/* Enable interrupts               */
 
 check_again:
 	p0.h = hi(PLL_STAT);
@@ -92,46 +92,46 @@ check_again:
 	if ! CC jump check_again;
 
 	/* Configure SCLK & CCLK Dividers */
-       	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
 
 	/*
-         * We now are running at speed, time to set the Async mem bank wait states
+	 * We now are running at speed, time to set the Async mem bank wait states
 	 * This will speed up execution, since we are normally running from FLASH.
 	 */
 
-        p2.h = (EBIU_AMBCTL1 >> 16);
-        p2.l = (EBIU_AMBCTL1 & 0xFFFF);
-        r0.h = (AMBCTL1VAL >> 16);
-        r0.l = (AMBCTL1VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMBCTL0 >> 16);
-        p2.l = (EBIU_AMBCTL0 & 0xFFFF);
-        r0.h = (AMBCTL0VAL >> 16);
-        r0.l = (AMBCTL0VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMGCTL >> 16);
-        p2.l = (EBIU_AMGCTL & 0xffff);
-        r0 = AMGCTLVAL;
-        w[p2] = r0;
-        ssync;
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+	
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+	
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
 
 	/*
 	 * Now, Initialize the SDRAM,
 	 * start with the SDRAM Refresh Rate Control Register
-         */
+	 */
 	p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
 
 	/*
 	 * SDRAM Memory Bank Control Register - bank specific parameters
@@ -147,29 +147,29 @@ check_again:
 	 * Disable self-refresh
 	 */
 	P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
 
 	/*
-         * Check if SDRAM is already powered up, if it is, enable self-refresh
-         */
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
 	p0.h = hi(EBIU_SDSTAT);
 	p0.l = lo(EBIU_SDSTAT);
 	r2.l = w[p0];
 	cc = bittst(r2,3);
 	if !cc jump skip;
-    	NOP;
+	NOP;
 	BITSET (R0, 23);
 skip:
 	[P2] = R0;
-        SSYNC;
+	SSYNC;
 
 	/* Write in the new value in the register */
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
 	[P2] = R0;
-        SSYNC;
+	SSYNC;
 	nop;
 
 	(P5:0) = [SP++];
@@ -177,4 +177,3 @@ skip:
 	RETS   = [SP++];
 	ASTAT  = [SP++];
 	RTS;
-
diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S
index 67074f9e69c..21cfeec33e6 100644
--- a/cpu/bf533/init_sdram_bootrom_initblock.S
+++ b/cpu/bf533/init_sdram_bootrom_initblock.S
@@ -28,17 +28,17 @@ init_sdram:
 	[--SP] = (R7:0);
 	[--SP] = (P5:0);
 
-#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) 
+#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
 	p0.h = hi(SPI_BAUD);
 	p0.l = lo(SPI_BAUD);
 	r0.l = CONFIG_SPI_BAUD_INITBLOCK;
 	w[p0] = r0.l;
-    SSYNC;
+	SSYNC;
 #endif
 
 	/*
-         * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
-         */
+	 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
+	 */
 	p0.h = hi(PLL_LOCKCNT);
 	p0.l = lo(PLL_LOCKCNT);
 	r0 = 0x300(Z);
@@ -46,43 +46,43 @@ init_sdram:
 	ssync;
 
 	/*
-         * Put SDRAM in self-refresh, incase anything is running
-         */
-        P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITSET (R0, 24);
-        [P2] = R0;
-        SSYNC;
-
-        /*
-         *  Set PLL_CTL with the value that we calculate in R0
-         *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
-         *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
-         *   - [7]     = output delay (add 200ps of delay to mem signals)
-         *   - [6]     = input delay (add 200ps of input delay to mem signals)
-         *   - [5]     = PDWN      : 1=All Clocks off
-         *   - [3]     = STOPCK    : 1=Core Clock off
-         *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
-         *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
-         *   all other bits set to zero
-         */
-
-        r0 = CONFIG_VCO_MULT & 63;      /* Load the VCO multiplier         */
-        r0 = r0 << 9;                   /* Shift it over,                  */
-        r1 = CONFIG_CLKIN_HALF;        /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = CONFIG_PLL_BYPASS;         /* Bypass the PLL?                 */
-        r1 = r1 << 8;                   /* Shift it over                   */
-        r0 = r1 | r0;                   /* add them all together           */
-
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);             /* Load the address                */
-        cli r2;                         /* Disable interrupts              */
+	 * Put SDRAM in self-refresh, incase anything is running
+	 */
+	P2.H = hi(EBIU_SDGCTL);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITSET (R0, 24);
+	[P2] = R0;
+	SSYNC;
+
+	/*
+	 *  Set PLL_CTL with the value that we calculate in R0
+	 *   - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
+	 *   - [8]     = BYPASS    : BYPASS the PLL, run CLKIN into CCLK/SCLK
+	 *   - [7]     = output delay (add 200ps of delay to mem signals)
+	 *   - [6]     = input delay (add 200ps of input delay to mem signals)
+	 *   - [5]     = PDWN      : 1=All Clocks off
+	 *   - [3]     = STOPCK    : 1=Core Clock off
+	 *   - [1]     = PLL_OFF   : 1=Disable Power to PLL
+	 *   - [0]     = DF        : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
+	 *   all other bits set to zero
+	 */
+
+	r0 = CONFIG_VCO_MULT & 63;	/* Load the VCO multiplier         */
+	r0 = r0 << 9;			/* Shift it over,                  */
+	r1 = CONFIG_CLKIN_HALF;		/* Do we need to divide CLKIN by 2?*/
+	r0 = r1 | r0;
+	r1 = CONFIG_PLL_BYPASS;		/* Bypass the PLL?                 */
+	r1 = r1 << 8;			/* Shift it over                   */
+	r0 = r1 | r0;			/* add them all together           */
+
+	p0.h = hi(PLL_CTL);
+	p0.l = lo(PLL_CTL);		/* Load the address                */
+	cli r2;				/* Disable interrupts              */
 	ssync;
-        w[p0] = r0.l;                   /* Set the value                   */
-        idle;                           /* Wait for the PLL to stablize    */
-        sti r2;                         /* Enable interrupts               */
+	w[p0] = r0.l;			/* Set the value                   */
+	idle;				/* Wait for the PLL to stablize    */
+	sti r2;				/* Enable interrupts               */
 
 check_again:
 	p0.h = hi(PLL_STAT);
@@ -92,46 +92,46 @@ check_again:
 	if ! CC jump check_again;
 
 	/* Configure SCLK & CCLK Dividers */
-       	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
+	r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
+	p0.h = hi(PLL_DIV);
+	p0.l = lo(PLL_DIV);
+	w[p0] = r0.l;
+	ssync;
 
 	/*
-         * We now are running at speed, time to set the Async mem bank wait states
+	 * We now are running at speed, time to set the Async mem bank wait states
 	 * This will speed up execution, since we are normally running from FLASH.
 	 */
 
-        p2.h = (EBIU_AMBCTL1 >> 16);
-        p2.l = (EBIU_AMBCTL1 & 0xFFFF);
-        r0.h = (AMBCTL1VAL >> 16);
-        r0.l = (AMBCTL1VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMBCTL0 >> 16);
-        p2.l = (EBIU_AMBCTL0 & 0xFFFF);
-        r0.h = (AMBCTL0VAL >> 16);
-        r0.l = (AMBCTL0VAL & 0xFFFF);
-        [p2] = r0;
-        ssync;
-
-        p2.h = (EBIU_AMGCTL >> 16);
-        p2.l = (EBIU_AMGCTL & 0xffff);
-        r0 = AMGCTLVAL;
-        w[p2] = r0;
-        ssync;
+	p2.h = (EBIU_AMBCTL1 >> 16);
+	p2.l = (EBIU_AMBCTL1 & 0xFFFF);
+	r0.h = (AMBCTL1VAL >> 16);
+	r0.l = (AMBCTL1VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+	
+	p2.h = (EBIU_AMBCTL0 >> 16);
+	p2.l = (EBIU_AMBCTL0 & 0xFFFF);
+	r0.h = (AMBCTL0VAL >> 16);
+	r0.l = (AMBCTL0VAL & 0xFFFF);
+	[p2] = r0;
+	ssync;
+	
+	p2.h = (EBIU_AMGCTL >> 16);
+	p2.l = (EBIU_AMGCTL & 0xffff);
+	r0 = AMGCTLVAL;
+	w[p2] = r0;
+	ssync;
 
 	/*
 	 * Now, Initialize the SDRAM,
 	 * start with the SDRAM Refresh Rate Control Register
-         */
+	 */
 	p0.l = lo(EBIU_SDRRC);
-        p0.h = hi(EBIU_SDRRC);
-        r0 = mem_SDRRC;
-        w[p0] = r0.l;
-        ssync;
+	p0.h = hi(EBIU_SDRRC);
+	r0 = mem_SDRRC;
+	w[p0] = r0.l;
+	ssync;
 
 	/*
 	 * SDRAM Memory Bank Control Register - bank specific parameters
@@ -147,35 +147,33 @@ check_again:
 	 * Disable self-refresh
 	 */
 	P2.H = hi(EBIU_SDGCTL);
-        P2.L = lo(EBIU_SDGCTL);
-        R0 = [P2];
-        BITCLR (R0, 24);
+	P2.L = lo(EBIU_SDGCTL);
+	R0 = [P2];
+	BITCLR (R0, 24);
 
 	/*
-         * Check if SDRAM is already powered up, if it is, enable self-refresh
-         */
+	 * Check if SDRAM is already powered up, if it is, enable self-refresh
+	 */
 	p0.h = hi(EBIU_SDSTAT);
 	p0.l = lo(EBIU_SDSTAT);
 	r2.l = w[p0];
 	cc = bittst(r2,3);
 	if !cc jump skip;
-    	NOP;
+	NOP;
 	BITSET (R0, 23);
 skip:
 	[P2] = R0;
-        SSYNC;
+	SSYNC;
 
 	/* Write in the new value in the register */
-        R0.L = lo(mem_SDGCTL);
-        R0.H = hi(mem_SDGCTL);
+	R0.L = lo(mem_SDGCTL);
+	R0.H = hi(mem_SDGCTL);
 	[P2] = R0;
-        SSYNC;
+	SSYNC;
 	nop;
 
-	
 	(P5:0) = [SP++];
 	(R7:0) = [SP++];
 	RETS   = [SP++];
 	ASTAT  = [SP++];
 	RTS;
-
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
index a5de96bba32..524da8f511c 100644
--- a/cpu/bf533/interrupt.S
+++ b/cpu/bf533/interrupt.S
@@ -95,7 +95,7 @@ _evt_rst:
 	sp += 12;
 
 _evt_rst_exit:
-	rtn; 
+	rtn;
 
 irq_panic:
 	r0 = IRQ_EVX;
@@ -134,7 +134,7 @@ _evt_evt7:
 
 evt_evt7_exit:
 	RESTORE_CONTEXT
-	rti; 
+	rti;
 
 .global _evt_evt8
 _evt_evt8:
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 8e2d725af2c..3a31e2f1115 100644
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -32,7 +32,7 @@
 
 /*
  * Note: A change in this file subsequently requires a change in
- *       board/$(board_name)/config.mk for a valid u-boot.bin 
+ *       board/$(board_name)/config.mk for a valid u-boot.bin
  */
 
 #define ASSEMBLY
@@ -152,10 +152,10 @@ no_soft_reset:
 	[ p0 ++ ] = r1;
 	
 	p0.h = hi(SIC_IWR);
-        p0.l = lo(SIC_IWR);
-        r0.l = 0x1;
-        w[p0] = r0.l;
-        SSYNC;
+	p0.l = lo(SIC_IWR);
+	r0.l = 0x1;
+	w[p0] = r0.l;
+	SSYNC;
 
 	sp.l = (0xffb01000 & 0xFFFF);
 	sp.h = (0xffb01000 >> 16);
diff --git a/cpu/bf533/video.c b/cpu/bf533/video.c
index 056564ab645..3ff0151d486 100644
--- a/cpu/bf533/video.c
+++ b/cpu/bf533/video.c
@@ -45,7 +45,7 @@ int is_vblank_line(const int line)
 {
 	/*
 	 *  This array contains a single bit for each line in
-	 *  an NTSC frame. 
+	 *  an NTSC frame.
 	 */
 	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
 		return true;
diff --git a/include/asm-blackfin/arch-bf533/anomaly.h b/include/asm-blackfin/arch-bf533/anomaly.h
index 0e5f9194386..4fe425c9c16 100644
--- a/include/asm-blackfin/arch-bf533/anomaly.h
+++ b/include/asm-blackfin/arch-bf533/anomaly.h
@@ -46,126 +46,126 @@
 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
 #if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
-                            slot1 and store of a P register in slot 2 is not
-                            supported */
+			    slot1 and store of a P register in slot 2 is not
+			    supported */
 #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
-                            every corresponding match */
+			    every corresponding match */
 #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
-                            Channel DMA stops */
+			    Channel DMA stops */
 #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
-                            registers. */
+			    registers. */
 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
-                            upper bits*/
+			    upper bits*/
 #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
-                            syncs */
+			    syncs */
 #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
-                            functional */
+			    functional */
 #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
-                            state */
+			    state */
 #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
-                            VDDint <=0.9V */
+			    VDDint <=0.9V */
 #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
-                            an edge is detected may clear interrupt */
+			    an edge is detected may clear interrupt */
 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
-                            DMA system instability */
+			    DMA system instability */
 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
-                            not restored */
+			    not restored */
 #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
-                            control */
+			    control */
 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
-                            killed in a particular stage*/
+			    killed in a particular stage*/
 #endif
 
 /* These issues only occur on 0.3 or 0.4 BF533 */
 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
 #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
-                            updated at the same time. */
+			    updated at the same time. */
 #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
-        		    Cache Fill can be corrupted after or during
-                            Instruction DMA if certain core stalls exist */
+			    Cache Fill can be corrupted after or during
+			    Instruction DMA if certain core stalls exist */
 #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
-                            Purpose TX or RX modes */
+			    Purpose TX or RX modes */
 #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
-                            preceding memory read */
+			    preceding memory read */
 #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
-                            inactive channels in certain conditions */
+			    inactive channels in certain conditions */
 #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
-                            situation */
+			    situation */
 #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
 #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
 #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
-                            data*/
+			    data*/
 #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
-                            Differences in certain Conditions */
+			    Differences in certain Conditions */
 #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
 #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
-                            hardware reset */
+			    hardware reset */
 #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
-                            IDLE around a Change of Control causes
-                            unpredictable results */
+			    IDLE around a Change of Control causes
+			    unpredictable results */
 #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
-                            shadow of a conditional branch */
+			    shadow of a conditional branch */
 #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
-                            errors */
+			    errors */
 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
 #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
-                            interrupt not functional */
+			    interrupt not functional */
 #define ANOMALY_05000257 /* An interrupt or exception during short Hardware
-                            loops may cause the instruction fetch unit to
-                            malfunction */
+			    loops may cause the instruction fetch unit to
+			    malfunction */
 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
-                            the ICPLB Data registers differ */
+			    the ICPLB Data registers differ */
 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
 #define ANOMALY_05000262 /* Stores to data cache may be lost */
 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
 #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
-                            instruction will cause an infinite stall in the
-                            second to last instruction in a hardware loop */
+			    instruction will cause an infinite stall in the
+			    second to last instruction in a hardware loop */
 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
-                            SPORT external receive and transmit clocks. */
+			    SPORT external receive and transmit clocks. */
 #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
-                            internal voltage regulator (VDDint) to increase. */
+			    internal voltage regulator (VDDint) to increase. */
 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
-                            internal voltage regulator (VDDint) to decrease */
+			    internal voltage regulator (VDDint) to decrease */
 #endif
 
 /* These issues are only on 0.4 silicon */
 #if (defined(CONFIG_BF_REV_0_4))
 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
-                            (TDM) */
+			    (TDM) */
 #endif
 
 /* These issues are only on 0.3 silicon */
 #if defined(CONFIG_BF_REV_0_3)
 #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
-                            External Frame Syncs */
+			    External Frame Syncs */
 #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
-                            Instruction or Data Fetches, or by Fetches at the
-                            boundary of reserved memory space */
+			    Instruction or Data Fetches, or by Fetches at the
+			    boundary of reserved memory space */
 #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
-                            when polarity setting is changed */
+			    when polarity setting is changed */
 #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
-                            corruption */
+			    corruption */
 #define ANOMALY_05000199 /* DMA current address shows wrong value during carry
-                            fix */
+			    fix */
 #define ANOMALY_05000201 /* Receive frame sync not ignored during active
-                            frames in sport MCM */
+			    frames in sport MCM */
 #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
-                            stopping */
+			    stopping */
 #if defined(CONFIG_BF533)
 #define ANOMALY_05000204 /* Incorrect data read with write-through cache and
-                            allocate cache lines on reads only mode */
+			    allocate cache lines on reads only mode */
 #endif /* CONFIG_BF533 */
 #define ANOMALY_05000207 /* Recovery from "brown-out" condition */
 #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
-                            instructions */
+			    instructions */
 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
-                            Sync Transmit Mode */
+			    Sync Transmit Mode */
 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
 #endif
 
diff --git a/include/asm-blackfin/arch-bf533/defBF532.h b/include/asm-blackfin/arch-bf533/defBF532.h
index 312ff2bf5c8..25a74e68466 100644
--- a/include/asm-blackfin/arch-bf533/defBF532.h
+++ b/include/asm-blackfin/arch-bf533/defBF532.h
@@ -88,7 +88,7 @@
 #define UART_LCR		0xFFC0040C	/* Line Control Register */
 #define UART_MCR		0xFFC00410	/* Modem Control Register */
 #define UART_LSR		0xFFC00414	/* Line Status Register */
-/* #define UART_MSR 0xFFC00418 *//* Modem Status Register (UNUSED in ADSP-BF532) */
+/* #define UART_MSR 0xFFC00418 */		/* Modem Status Register (UNUSED in ADSP-BF532) */
 #define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
 #define UART_GCTL		0xFFC00424	/* Global Control Register */
 
diff --git a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
index f82ccbe4ec2..90b21e525ba 100644
--- a/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/arch-common/cdef_LPBlackfin.h
@@ -14,14 +14,11 @@
 #endif
 #include <asm/arch-common/def_LPBlackfin.h>
 
-// Cache & SRAM Memory
+/* Cache & SRAM Memory	*/
 #define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
 #define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
 #define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
 #define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
-/*
-#define MMR_TIMEOUT            0xFFE00010  // Memory-Mapped Register Timeout Register
-*/
 #define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
 #define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
 #define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@@ -55,15 +52,8 @@
 #define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
 #define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
 #define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-/*
-#define DTEST_INDEX            0xFFE00304  // Data Test Index Register
-*/
 #define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
 #define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-/*
-#define DTEST_DATA2            0xFFE00408  // Data Test Data Register
-#define DTEST_DATA3            0xFFE0040C  // Data Test Data Register
-*/
 #define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
 #define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
 #define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@@ -100,13 +90,10 @@
 #define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
 #define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
 #define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-/*
-#define ITEST_INDEX            0xFFE01304  // Instruction Test Index Register
-*/
 #define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
 #define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
 
-// Event/Interrupt Registers
+/* Event/Interrupt Registers */
 #define pEVT0 ((volatile void **)EVT0)
 #define pEVT1 ((volatile void **)EVT1)
 #define pEVT2 ((volatile void **)EVT2)
@@ -127,24 +114,24 @@
 #define pIPEND ((volatile unsigned long *)IPEND)
 #define pILAT ((volatile unsigned long *)ILAT)
 
-// Core Timer Registers
+/* Core Timer Registers */
 #define pTCNTL ((volatile unsigned long *)TCNTL)
 #define pTPERIOD ((volatile unsigned long *)TPERIOD)
 #define pTSCALE ((volatile unsigned long *)TSCALE)
 #define pTCOUNT ((volatile unsigned long *)TCOUNT)
 
-// Debug/MP/Emulation Registers
+/* Debug/MP/Emulation Registers */
 #define pDSPID ((volatile unsigned long *)DSPID)
 #define pDBGCTL ((volatile unsigned long *)DBGCTL)
 #define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
 #define pEMUDAT ((volatile unsigned long *)EMUDAT)
 
-// Trace Buffer Registers
+/* Trace Buffer Registers */
 #define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
 #define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
 #define pTBUF ((volatile void **)TBUF)
 
-// Watch Point Control Registers
+/* Watch Point Control Registers */
 #define pWPIACTL ((volatile unsigned long *)WPIACTL)
 #define pWPIA0 ((volatile void **)WPIA0)
 #define pWPIA1 ((volatile void **)WPIA1)
@@ -165,13 +152,9 @@
 #define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
 #define pWPSTAT ((volatile unsigned long *)WPSTAT)
 
-// Performance Monitor Registers
+/* Performance Monitor Registers */
 #define pPFCTL ((volatile unsigned long *)PFCTL)
 #define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
 #define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
 
-/*
-#define IPRIO                  0xFFE02110  // Core Interrupt Priority Register
-*/
-
 #endif /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h
index a9baacdfb84..d9d8bf9ba25 100644
--- a/include/asm-blackfin/mem_init.h
+++ b/include/asm-blackfin/mem_init.h
@@ -26,7 +26,7 @@
 	CONFIG_MEM_MT48LC64M4A2FB_7E || \
 	CONFIG_MEM_MT48LC16M8A2TG_75 || \
 	CONFIG_MEM_MT48LC8M16A2TG_7E || \
-  CONFIG_MEM_MT48LC8M32B2B5_7  || \
+	CONFIG_MEM_MT48LC8M32B2B5_7  || \
 	CONFIG_MEM_MT48LC32M8A2_75)
 
 	#if ( CONFIG_SCLK_HZ > 119402985 )
@@ -105,43 +105,43 @@
 
 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	8192     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	8192	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_2
 #endif
 
 #if (CONFIG_MEM_MT48LC16M8A2TG_75)
-        /*SDRAM INFORMATION: */
-        #define SDRAM_Tref      64       /* Refresh period in milliseconds   */
-        #define SDRAM_NRA       4096     /* Number of row addresses in SDRAM */
-        #define SDRAM_CL        CL_3
+	/*SDRAM INFORMATION: */
+	#define SDRAM_Tref      64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA       4096	/* Number of row addresses in SDRAM */
+	#define SDRAM_CL        CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64		/* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */
+/*SDRAM INFORMATION: */
+#define SDRAM_Tref  64			/* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192		/* Number of row addresses in SDRAM */
 #define SDRAM_CL    CL_3
 #endif
 
 #if (CONFIG_MEM_MT48LC8M16A2TG_7E)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_2
 #endif
 
 #if (CONFIG_MEM_MT48LC8M32B2B5_7)
 	/*SDRAM INFORMATION: */
-	#define SDRAM_Tref	64       /* Refresh period in milliseconds   */
-	#define SDRAM_NRA	4096     /* Number of row addresses in SDRAM */
+	#define SDRAM_Tref	64	/* Refresh period in milliseconds   */
+	#define SDRAM_NRA	4096	/* Number of row addresses in SDRAM */
 	#define SDRAM_CL	CL_3
 #endif
 
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 7afc1a17fe1..3e165f24956 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -9,13 +9,13 @@
 #define CONFIG_STAMP		1
 
 #define CONFIG_BOOTDELAY	5
-#define CFG_AUTOLOAD                    "no"    /*rarpb, bootp or dhcp commands will perform only a */
+#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
 
-#define CFG_LONGHELP                    1
+#define CFG_LONGHELP		1
 #define CONFIG_CMDLINE_EDITING	1
-#define CONFIG_LOADADDR		0x01000000      /* default load address */
+#define CONFIG_LOADADDR		0x01000000	/* default load address */
 #define CONFIG_BOOTCOMMAND	"tftp $(loadaddr) linux"
-//#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
+/* #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw" */
 
 #define CONFIG_DRIVER_SMC91111	1
 #define CONFIG_SMC91111_BASE	0x20310300
@@ -32,12 +32,12 @@
  * Boot Mode Set
  * Blackfin can support several boot modes
  */
-#define BF533_BYPASS_BOOT	0x0001  /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT		0x0002  /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash		*/
+#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
 /* Define the boot mode */
 #define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
-//#define BFIN_BOOT_MODE		BF533_SPI_BOOT
+/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
 
 #define CONFIG_PANIC_HANG 1
 
@@ -53,46 +53,46 @@
 /* Define where the uboot will be loaded by on-chip boot rom */
 #define APP_ENTRY 0x00001000
 
-/* CONFIG_CLKIN_HZ is any value in Hz                            */
-#define CONFIG_CLKIN_HZ          27000000
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
-/*                                                  1=CLKIN/2    */
-#define CONFIG_CLKIN_HALF               0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
-/*                                               1=bypass PLL    */
-#define CONFIG_PLL_BYPASS               0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
-/* Values can range from 1-64                                    */
-#define CONFIG_VCO_MULT			22
-/* CONFIG_CCLK_DIV controls what the core clock divider is       */
-/* Values can be 1, 2, 4, or 8 ONLY                              */
-#define CONFIG_CCLK_DIV			1
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		27000000
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
+/*						 1=bypass PLL	*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT		22
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV		1
 /* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15                                    */
-#define CONFIG_SCLK_DIV			5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider     */
-/* Values can range from 2-65535                                 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                  */
-#define CONFIG_SPI_BAUD                 2
-#define CONFIG_SPI_BAUD_INITBLOCK		4
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV		5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
+#define CONFIG_SPI_BAUD_INITBLOCK	4
 
 #if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ           ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
 #else
-#define CONFIG_VCO_HZ           (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
 #endif
 
 #if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ          ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
 #else
-#define CONFIG_CCLK_HZ          CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ          CONFIG_CLKIN_HZ
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
 #endif
 
-#define CONFIG_MEM_SIZE                 32             /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH              9             /* 8, 9, 10, 11    */
-#define CONFIG_MEM_MT48LC16M16A2TG_75    1
+#define CONFIG_MEM_SIZ		32	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	9	/* 8, 9, 10, 11    */
+#define CONFIG_MEM_MT48LC16M16A2TG_75	1
 
 #define CONFIG_LOADS_ECHO	1
 
@@ -146,16 +146,16 @@
 #define	CFG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
 
 /* JFFS Partition offset set  */
-#define CFG_JFFS2_FIRST_BANK 0
-#define CFG_JFFS2_NUM_BANKS  1
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR                 11
+#define CFG_JFFS2_FIRST_SECTOR	11
 
 
 /*
  * Stack sizes
  */
-#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 
 #define POLL_MODE		1
 #define FLASH_TOT_SECT		40
@@ -171,50 +171,50 @@
  * I2C settings
  * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
  */
-#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged */
 /*
  * Software (bit-bang) I2C driver configuration
  */
-#define PF_SCL				PF0
-#define PF_SDA				PF1
-
-#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SDA; \
-							asm("ssync;"); \
-						} \
-					else    { \
-							*pFIO_FLAG_C = PF_SDA; \
-							asm("ssync;"); \
-						}
-#define I2C_SCL(bit)			if(bit) { \
-							*pFIO_FLAG_S = PF_SCL; \
-							asm("ssync;"); \
-						} \
-					else    { \
-							*pFIO_FLAG_C = PF_SCL; \
-							asm("ssync;"); \
-						}
-#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED			50000
-#define CFG_I2C_SLAVE			0xFE
+#define PF_SCL			PF0
+#define PF_SDA			PF1
+
+#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SDA; \
+				asm("ssync;"); \
+				} \
+			else    { \
+				*pFIO_FLAG_C = PF_SDA; \
+				asm("ssync;"); \
+				}
+#define I2C_SCL(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SCL; \
+				asm("ssync;"); \
+				} \
+			else    { \
+				*pFIO_FLAG_C = PF_SCL; \
+				asm("ssync;"); \
+				}
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0xFE
 
 #define CFG_BOOTM_LEN		0x4000000	/* Large Image Length, set to 64 Meg */
 
 /* 0xFF, 0x7BB07BB0, 0x22547BB0 */
-/* #define AMGCTLVAL            (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL              (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL |    \
-                                ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
-#define AMBCTL1VAL              (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN |   \
-                                B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
+/* #define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
+				~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
+#define AMBCTL1VAL		(B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
+				B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
 */
-#define AMGCTLVAL               0xFF
-#define AMBCTL0VAL              0x7BB07BB0
-#define AMBCTL1VAL              0xFFC27BB0
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0x7BB07BB0
+#define AMBCTL1VAL		0xFFC27BB0
 
 #define CONFIG_VDSP		1
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 353a43c286a..cde2c245c87 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -12,12 +12,12 @@
  * Boot Mode Set
  * Blackfin can support several boot modes
  */
-#define BF533_BYPASS_BOOT	0x0001  /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
-#define BF533_PARA_BOOT		0x0002  /* Bootmode 1: Boot from 8-bit or 16-bit flash */
-#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash		*/
+#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
+#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
+#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
 /* Define the boot mode */
 #define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
-//#define BFIN_BOOT_MODE		BF533_SPI_BOOT
+/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */
 
 #define CONFIG_PANIC_HANG 1
 
@@ -41,65 +41,61 @@
 
 /*
  * Board settings
- *
  */
-#define CONFIG_DRIVER_SMC91111          1
-#define CONFIG_SMC91111_BASE            0x20300300
+#define CONFIG_DRIVER_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20300300
 
 /* FLASH/ETHERNET uses the same address range */
-#define SHARED_RESOURCES 		1
+#define SHARED_RESOURCES 	1
 
 /* Is I2C bit-banged? */
-#define CONFIG_SOFT_I2C                 1
+#define CONFIG_SOFT_I2C		1
 
 /*
  * Software (bit-bang) I2C driver configuration
  */
-#define PF_SCL                          PF3
-#define PF_SDA                          PF2
+#define PF_SCL			PF3
+#define PF_SDA			PF2
 
 /*
  * Video splash screen support
  */
-#define  CONFIG_VIDEO			0
+#define  CONFIG_VIDEO		0
 
-#define CONFIG_VDSP			1
+#define CONFIG_VDSP		1
 
 /*
  * Clock settings
- *
  */
 
-/* CONFIG_CLKIN_HZ is any value in Hz                            */
-#define CONFIG_CLKIN_HZ			11059200
-/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN      */
-/*                                                  1=CLKIN/2    */
-#define CONFIG_CLKIN_HALF		0
-/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass  */
-/*                                               1=bypass PLL    */
-#define CONFIG_PLL_BYPASS       	0
-/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.   */
-/* Values can range from 1-64                                    */
-#define CONFIG_VCO_MULT			36
-/* CONFIG_CCLK_DIV controls what the core clock divider is       */
-/* Values can be 1, 2, 4, or 8 ONLY                              */
-#define CONFIG_CCLK_DIV			1
-/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
-/* Values can range from 1-15                                    */
-#define CONFIG_SCLK_DIV			5
-/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider     */
-/* Values can range from 2-65535                                 */
-/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)                  */
-#define CONFIG_SPI_BAUD                 2
+/* CONFIG_CLKIN_HZ is any value in Hz				*/
+#define CONFIG_CLKIN_HZ		11059200
+/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
+/*						    1=CLKIN/2	*/
+#define CONFIG_CLKIN_HALF	0
+/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
+/*						 1=bypass PLL	*/
+#define CONFIG_PLL_BYPASS	0
+/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
+/* Values can range from 1-64					*/
+#define CONFIG_VCO_MULT		36
+/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
+/* Values can be 1, 2, 4, or 8 ONLY				*/
+#define CONFIG_CCLK_DIV		1
+/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
+/* Values can range from 1-15					*/
+#define CONFIG_SCLK_DIV		5
+/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
+/* Values can range from 2-65535				*/
+/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
+#define CONFIG_SPI_BAUD		2
 
 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_SPI_BAUD_INITBLOCK		4
+#define CONFIG_SPI_BAUD_INITBLOCK	4
 #endif
 
-
 /*
  * Network settings
- *
  */
 
 #if (CONFIG_DRIVER_SMC91111)
@@ -108,92 +104,90 @@
 #endif
 
 /* network support */
-#define CONFIG_IPADDR           192.168.0.15
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_GATEWAYIP        192.168.0.1
-#define CONFIG_SERVERIP         192.168.0.2
-#define CONFIG_HOSTNAME         STAMP
-#define CONFIG_ROOTPATH                 /checkout/uClinux-dist/romfs
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		STAMP
+#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs
 
 /* To remove hardcoding and enable MAC storage in EEPROM  */
-/* #define CONFIG_ETHADDR               02:80:ad:20:31:b8 */
+/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
 #endif /* CONFIG_DRIVER_SMC91111 */
 
 /*
  * Flash settings
- *
  */
 
-#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
-#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
 #define	CFG_FLASH_CFI_AMD_RESET
 
-#define CFG_FLASH_BASE			0x20000000
-#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks */
-#define CFG_MAX_FLASH_SECT		67		/* max number of sectors on one chip */
+#define CFG_FLASH_BASE		0x20000000
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_ENV_IS_IN_FLASH		1
-#define CFG_ENV_ADDR			0x20004000
-#define	CFG_ENV_OFFSET			(CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20004000
+#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CFG_ENV_IS_IN_EEPROM		1
-#define CFG_ENV_OFFSET			0x4000
-#define CFG_ENV_HEADER			(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
 #endif
 
-#define	CFG_ENV_SIZE			0x2000
-#define CFG_ENV_SECT_SIZE 		0x2000	/* Total Size of Environment Sector */
+#define	CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
 #define	ENV_IS_EMBEDDED
 
-#define CFG_FLASH_ERASE_TOUT		30000	/* Timeout for Chip Erase (in ms) */
+#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
 #define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT		1	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */
 
 /* JFFS Partition offset set  */
 #define CFG_JFFS2_FIRST_BANK 0
 #define CFG_JFFS2_NUM_BANKS  1
 /* 512k reserved for u-boot */
-#define CFG_JFFS2_FIRST_SECTOR 		11
+#define CFG_JFFS2_FIRST_SECTOR 	11
 
 /*
  * following timeouts shall be used once the
  * Flash real protection is enabled
  */
-#define CFG_FLASH_LOCK_TOUT		5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT		10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
 
 /*
  * SDRAM settings & memory map
- *
  */
 
-#define CONFIG_MEM_SIZE			128             /* 128, 64, 32, 16 */
-#define CONFIG_MEM_ADD_WDTH     	11             /* 8, 9, 10, 11    */
+#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
 #define CONFIG_MEM_MT48LC64M4A2FB_7E	1
 
 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_MEMTEST_START		0x00000000	/* memtest works on */
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CFG_MEMTEST_START		0x00100000	/* memtest works on */
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
 #endif
 
-#define	CFG_SDRAM_BASE			0x00000000
+#define	CFG_SDRAM_BASE		0x00000000
 
 #define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
 #define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
 #define CONFIG_LOADADDR		0x01000000
 
-#define CFG_LOAD_ADDR 			CONFIG_LOADADDR
-#define	CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN                  (128 << 10)     /* Reserve 128 kB for malloc()  */
-#define CFG_GBL_DATA_SIZE               0x4000		/* Reserve 16k for Global Data  */
-#define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
+#define CFG_LOAD_ADDR 		CONFIG_LOADADDR
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
+#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
 
 #define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
-#define CFG_MALLOC_BASE                 (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
-#define CFG_GBL_DATA_ADDR               (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
-#define CONFIG_STACKBASE                (CFG_GBL_DATA_ADDR  - 4)
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)
 
 /* Check to make sure everything fits in SDRAM */
 #if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
@@ -201,17 +195,17 @@
 #endif
 
 #if ( CONFIG_CLKIN_HALF == 0 )
-#define CONFIG_VCO_HZ			( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
+#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
 #else
-#define CONFIG_VCO_HZ			(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
+#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
 #endif
 
 #if (CONFIG_PLL_BYPASS == 0)
-#define CONFIG_CCLK_HZ			( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
-#define CONFIG_SCLK_HZ			( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
+#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
+#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
 #else
-#define CONFIG_CCLK_HZ			CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ			CONFIG_CLKIN_HZ
+#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
 #endif
 
 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
@@ -221,71 +215,71 @@
 #undef CONFIG_SPI_FLASH_FAST_READ
 #endif
 #endif
+
 /*
  * Command settings
- *
  */
 
-#define CFG_LONGHELP                    1
-#define CONFIG_CMDLINE_EDITING          1
+#define CFG_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
 
 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CFG_AUTOLOAD                    "no"    /*rarpb, bootp or dhcp commands will perform only a */
+#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
 #endif
-                                                /* configuration lookup from the BOOTP/DHCP server, */
-                                                /* but not try to load any image using TFTP         */
 
-#define CONFIG_BOOTDELAY                5
-#define CONFIG_BOOT_RETRY_TIME          -1      /* Enable this if bootretry required, currently its disabled */
+/* configuration lookup from the BOOTP/DHCP server, */
+/* but not try to load any image using TFTP         */
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
-#define CONFIG_BOOTCOMMAND              "run ramboot"
+#define CONFIG_BOOTCOMMAND	"run ramboot"
 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
-#define CONFIG_BOOTCOMMAND 		"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
+#define CONFIG_BOOTCOMMAND 	"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
 #endif
 
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"
 
 #if (CONFIG_DRIVER_SMC91111)
-#define CONFIG_COMMANDS1                (CONFIG_CMD_DFL | \
-                                         CFG_CMD_PING   | \
-                                         CFG_CMD_ELF    | \
-                                         CFG_CMD_CACHE  | \
-                                         CFG_CMD_JFFS2  | \
-                                         CFG_CMD_EEPROM | \
-                                         CFG_CMD_DATE)
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL | \
+				 CFG_CMD_PING   | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2  | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DATE)
 
 #else
-#define CONFIG_COMMANDS1                (CONFIG_CMD_DFL | \
-                                         CFG_CMD_ELF    | \
-                                         CFG_CMD_CACHE  | \
-                                         CFG_CMD_JFFS2  | \
-                                         CFG_CMD_EEPROM | \
-                                         CFG_CMD_DATE)
-
+#define CONFIG_COMMANDS1	(CONFIG_CMD_DFL | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_CACHE  | \
+				 CFG_CMD_JFFS2  | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DATE)
 #endif
 
 #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
 #if (CONFIG_DRIVER_SMC91111)
 #define CONFIG_EXTRA_ENV_SETTINGS \
-        "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
-        "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
-                "$(rootpath) console=ttyBF0,57600\0" \
-        "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
-                "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
-        "ramboot=tftpboot $(loadaddr) linux; " \
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
+		"$(rootpath) console=ttyBF0,57600\0" \
+	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
+		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux; " \
 		"run ramargs;run addip;bootelf\0" \
-        "nfsboot=tftpboot $(loadaddr) linux; " \
+	"nfsboot=tftpboot $(loadaddr) linux; " \
 		"run nfsargs;run addip;bootelf\0" \
-        "flashboot=bootm 0x20100000\0" \
-        "update=tftpboot $(loadaddr) u-boot.bin; " \
-                "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
-                "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
-        ""
+	"flashboot=bootm 0x20100000\0" \
+	"update=tftpboot $(loadaddr) u-boot.bin; " \
+		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
+	""
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
-        "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
-        "flashboot=bootm 0x20100000\0" \
-        ""
+	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
+	"flashboot=bootm 0x20100000\0" \
+	"
 #endif
 
 #elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
@@ -328,40 +322,39 @@
 
 /*
  * Console settings
- *
  */
 
-#define CONFIG_BAUDRATE                 57600
-#define CFG_BAUDRATE_TABLE              { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE		57600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 #if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
 #if (BFIN_CPU == ADSP_BF531)
-#define	CFG_PROMPT		"serial_bf531> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"serial_bf531> "	/* Monitor Command Prompt */
 #elif (BFIN_CPU == ADSP_BF532)
-#define	CFG_PROMPT		"serial_bf532> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"serial_bf532> "	/* Monitor Command Prompt */
 #else
-#define	CFG_PROMPT		"serial_bf533> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"serial_bf533> "	/* Monitor Command Prompt */
 #endif
 #else
 #if (BFIN_CPU == ADSP_BF531)
-#define	CFG_PROMPT		"bf531> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"bf531> "	/* Monitor Command Prompt */
 #elif (BFIN_CPU == ADSP_BF532)
-#define	CFG_PROMPT		"bf532> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"bf532> "	/* Monitor Command Prompt */
 #else
-#define	CFG_PROMPT		"bf533> "	/* Monitor Command Prompt */
+#define	CFG_PROMPT	"bf533> "	/* Monitor Command Prompt */
 #endif
 #endif
 
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE                      1024    /* Console I/O Buffer Size */
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-#define CFG_CBSIZE                      256     /* Console I/O Buffer Size */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
-#define CFG_PBSIZE                      (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)      /* Print Buffer Size */
-#define CFG_MAXARGS                     16      /* max number of command args */
-#define CFG_BARGSIZE                    CFG_CBSIZE      /* Boot Argument Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
 
-#define CONFIG_LOADS_ECHO               1
+#define CONFIG_LOADS_ECHO	1
 
 /*
  * I2C settings
@@ -369,30 +362,30 @@
  */
 #if (CONFIG_SOFT_I2C)
 
-#define I2C_INIT                        (*pFIO_DIR |=  PF_SCL); asm("ssync;")
-#define I2C_ACTIVE                      (*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
-#define I2C_TRISTATE                    (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
-#define I2C_READ                        ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
-#define I2C_SDA(bit)                    if(bit) { \
-                                                        *pFIO_FLAG_S = PF_SDA; \
-                                                        asm("ssync;"); \
-                                                } \
-                                        else    { \
-                                                        *pFIO_FLAG_C = PF_SDA; \
-                                                        asm("ssync;"); \
-                                                }
-#define I2C_SCL(bit)                    if(bit) { \
-                                                        *pFIO_FLAG_S = PF_SCL; \
-                                                        asm("ssync;"); \
-                                                } \
-                                        else    { \
-                                                        *pFIO_FLAG_C = PF_SCL; \
-                                                        asm("ssync;"); \
-                                                }
-#define I2C_DELAY                       udelay(5)       /* 1/4 I2C clock duration */
-
-#define CFG_I2C_SPEED                   50000
-#define CFG_I2C_SLAVE                   0xFE
+#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
+#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
+#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
+#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
+#define I2C_SDA(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SDA; \
+				asm("ssync;"); \
+				} \
+			else	{ \
+				*pFIO_FLAG_C = PF_SDA; \
+				asm("ssync;"); \
+				}
+#define I2C_SCL(bit)	if(bit) { \
+				*pFIO_FLAG_S = PF_SCL; \
+				asm("ssync;"); \
+				} \
+			else	{ \
+				*pFIO_FLAG_C = PF_SCL; \
+				asm("ssync;"); \
+				}
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED		50000
+#define CFG_I2C_SLAVE		0xFE
 #endif /* CONFIG_SOFT_I2C */
 
 /*
@@ -400,48 +393,48 @@
  */
 
 /* Enabled below option for CF support */
-/* #define CONFIG_STAMP_CF              1 */
+/* #define CONFIG_STAMP_CF	1 */
 
 #if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
 
-#define CONFIG_MISC_INIT_R              1
-#define CONFIG_DOS_PARTITION            1
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_DOS_PARTITION	1
 /*
  * IDE/ATA stuff
  */
-#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported */
+#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED			/* no led for ide supported */
+#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
 
-#define CFG_IDE_MAXBUS  1               /* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE               (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR               0x20200000
-#define CFG_ATA_IDE0_OFFSET             0x0000
+#define CFG_ATA_BASE_ADDR	0x20200000
+#define CFG_ATA_IDE0_OFFSET	0x0000
 
-#define CFG_ATA_DATA_OFFSET             0x0020  /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET              0x0020  /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET              0x0007  /* Offset for alternate registers */
+#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */
 
-#define CFG_ATA_STRIDE                  2
+#define CFG_ATA_STRIDE		2
 #endif
 
 /*
  * Miscellaneous configurable options
  */
 
-#define	CFG_HZ				1000		/* 1ms time tick */
+#define	CFG_HZ			1000	/* 1ms time tick */
 
-#define CFG_BOOTM_LEN			0x4000000	/* Large Image Length, set to 64 Meg */
+#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */
 
-#define CONFIG_SHOW_BOOT_PROGRESS	1	/* Show boot progress on LEDs */
+#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */
 
 #define CONFIG_SPI
 
 #ifdef  CONFIG_VIDEO
 #if (CONFIG_VIDEO)
-#define CONFIG_SPLASH_SCREEN		1
-#define CONFIG_SILENT_CONSOLE		1
+#define CONFIG_SPLASH_SCREEN	1
+#define CONFIG_SILENT_CONSOLE	1
 #else
 #undef CONFIG_VIDEO
 #endif
@@ -450,19 +443,19 @@
 /*
  * FLASH organization and environment definitions
  */
-#define	CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */
+#define	CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */
 
 /* 0xFF, 0xBBC3BBc3, 0x99B39983 */
-/*#define AMGCTLVAL             (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
-#define AMBCTL0VAL              (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |    \
-                                B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
-#define AMBCTL1VAL              (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |      \
-                                B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
+/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
+#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
+				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
+#define AMBCTL1VAL   		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
+				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
 */
-#define AMGCTLVAL               0xFF
-#define AMBCTL0VAL              0xBBC3BBC3
-#define AMBCTL1VAL              0x99B39983
-#define CF_AMBCTL1VAL           0x99B3ffc2
+#define AMGCTLVAL		0xFF
+#define AMBCTL0VAL		0xBBC3BBC3
+#define AMBCTL1VAL		0x99B39983
+#define CF_AMBCTL1VAL		0x99B3ffc2
 
 #ifdef CONFIG_VDSP
 #define ET_EXEC_VDSP		0x8
@@ -471,5 +464,4 @@
 #define VDSP_ENTRY_ADDR		0xFFA00000
 #endif
 
-
 #endif
diff --git a/lib_blackfin/memcpy.S b/lib_blackfin/memcpy.S
index a80fe3dd04a..a73ff90712e 100644
--- a/lib_blackfin/memcpy.S
+++ b/lib_blackfin/memcpy.S
@@ -33,9 +33,6 @@
  * to the Free Software Foundation, Inc.,
  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
-
-
-
 .align 2
 
 .globl _memcpy_ASM;