PCIe, USB: Replace 'end point' references with 'endpoint'

When referring to PCIe and USB 'endpoint' is the standard naming
convention.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>

16 files changed, 40 insertions, 40 deletions

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 67a016787a4..8c65cfb6fe5 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -609,7 +609,7 @@ int board_pcie_card_present(int port)
 /*
  * For the given slot, set endpoint mode, send power to the slot,
  * turn on the green LED and turn off the yellow LED, enable the
- * clock. In end point mode reset bit is read only.
+ * clock. In endpoint mode reset bit is read only.
  */
 void board_pcie_setup_port(int port, int rootpoint)
 {
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index da6cf47433d..c11a5c34995 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -219,7 +219,7 @@ void pci_init_board(void)
 		pcie1_hose.region_count = 1;
 #endif
 		printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index f8292cf3789..81a56b55e0b 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -226,7 +226,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
-			pcie_ep ? "End Point" : "Root Complex",
+			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie3_hose, first_free_busno);
@@ -246,7 +246,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
-			pcie_ep ? "End Point" : "Root Complex",
+			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
@@ -266,7 +266,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
-			pcie_ep ? "End Point" : "Root Complex",
+			pcie_ep ? "Endpoint" : "Root Complex",
 			pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 35a8063c9bf..b35e02f6855 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -144,7 +144,7 @@ void pci_init_board(void)
 		pcie3_hose.region_count = 1;
 #endif
 		printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie3_hose, first_free_busno);
@@ -179,7 +179,7 @@ void pci_init_board(void)
 		pcie1_hose.region_count = 1;
 #endif
 		printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
@@ -210,7 +210,7 @@ void pci_init_board(void)
 		pcie2_hose.region_count = 1;
 #endif
 		printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 38cbc8bac1b..aa3f32bf678 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -343,7 +343,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 60e22de4b96..4ec13a96914 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -408,7 +408,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 56854caa8d4..1c76b84efc1 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -552,7 +552,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 64e164b1a0d..74085c3260e 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -194,7 +194,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf ("    PCIE3 connected to ULI as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie3_hose, first_free_busno);
@@ -226,7 +226,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
@@ -246,7 +246,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 2d4b9addb67..784a2ed686d 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -249,7 +249,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf ("    PCIE1 connected to ULI as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
@@ -270,7 +270,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf ("    PCIE2 connected to Slot as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 6fd6963f0cf..aa2f64ca910 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -66,7 +66,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf("    PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
@@ -85,7 +85,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 599caa235d1..f6eae55d1d6 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -222,7 +222,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 2);
 		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 		printf("    PCIE2 connected to ULI as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie2_hose, first_free_busno);
@@ -262,7 +262,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 3);
 		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 		printf("    PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie3_hose, first_free_busno);
@@ -281,7 +281,7 @@ void pci_init_board(void)
 		SET_STD_PCIE_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 		printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
+				pcie_ep ? "Endpoint" : "Root Complex",
 				pci_info[num].regs);
 		first_free_busno = fsl_pci_init_port(&pci_info[num++],
 					&pcie1_hose, first_free_busno);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index aa7827e1ec6..8c9d586925a 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -636,7 +636,7 @@ static inline void init_pcie1(void)
 
 	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
 		printf ("PCIe:  %s, base address %x",
-			pcie_ep ? "End point" : "Root complex", (uint)pci);
+			pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
 
 		if (pci->pme_msg_det) {
 			pci->pme_msg_det = 0xffffffff;
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index a6158206516..3a8182715be 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -256,7 +256,7 @@ void pci_init_board(void)
 
 	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
 		printf("\n    PCIE1 connected as %s (x%d)",
-			host ? "Root Complex" : "End Point", width);
+			host ? "Root Complex" : "Endpoint", width);
 		if (in_be32(&pci->pme_msg_det)) {
 			out_be32(&pci->pme_msg_det, 0xffffffff);
 			debug(" with errors.  Clearing.  Now 0x%08x",
@@ -305,7 +305,7 @@ void pci_init_board(void)
 
 	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
 		printf("\n    PCIE2 connected as %s (x%d)",
-			host ? "Root Complex" : "End Point", width);
+			host ? "Root Complex" : "Endpoint", width);
 		if (in_be32(&pci->pme_msg_det)) {
 			out_be32(&pci->pme_msg_det, 0xffffffff);
 			debug(" with errors.  Clearing.  Now 0x%08x",
@@ -354,7 +354,7 @@ void pci_init_board(void)
 
 	if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
 		printf("\n    PCIE3 connected as %s (x%d)",
-			host ? "Root Complex" : "End Point", width);
+			host ? "Root Complex" : "Endpoint", width);
 		if (in_be32(&pci->pme_msg_det)) {
 			out_be32(&pci->pme_msg_det, 0xffffffff);
 			debug(" with errors.  Clearing.  Now 0x%08x",
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index d9605c30b50..f3b921477bf 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -924,7 +924,7 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
 }
 
 /*
- *  4xx boards as end point and root point setup
+ *  4xx boards as endpoint and root point setup
  *                    and
  *    testing inbound and out bound windows
  *
@@ -940,7 +940,7 @@ static inline u64 ppc4xx_get_cfgaddr(int port)
  *
  *  Once your board came up as root point , you can verify by reading
  *  /proc/bus/pci/devices. Where you can see the configuration registers
- *  of end point device attached to the port.
+ *  of endpoint device attached to the port.
  *
  *  Enpoint cofiguration can be verified by connecting 4xx board to any
  *  host or another 4xx board. Then try to scan the device. In case of
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index f0f0301bd1f..9a1fb4f316c 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -133,7 +133,7 @@ struct musb_regs {
 		u8	rxhubport;
 	} tar[16];
 	/*
-	 * end point registers
+	 * endpoint registers
 	 * ep0 elements are valid when array index is 0
 	 * otherwise epN is valid
 	 */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 3b994562273..f48945a27a2 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -112,7 +112,7 @@ struct usb_ehci {
 	u32	perlistbase;	/* 0x154 - Periodic List Base
 					 - USB Device Address */
 	u32	ep_list_addr;	/* 0x158 - Next Asynchronous List
-					 - End Point Address */
+					 - Endpoint Address */
 	u8	res5[0x4];
 	u32	burstsize;	/* 0x160 - Programmable Burst Size */
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
@@ -124,17 +124,17 @@ struct usb_ehci {
 	u32	portsc;		/* 0x184 - Port status/control */
 	u8	res8[0x20];
 	u32	usbmode;	/* 0x1a8 - USB Device Mode */
-	u32	epsetupstat;	/* 0x1ac - End Point Setup Status */
-	u32	epprime;	/* 0x1b0 - End Point Init Status */
-	u32	epflush;	/* 0x1b4 - End Point De-initlialize */
-	u32	epstatus;	/* 0x1b8 - End Point Status */
-	u32	epcomplete;	/* 0x1bc - End Point Complete */
-	u32	epctrl0;	/* 0x1c0 - End Point Control 0 */
-	u32	epctrl1;	/* 0x1c4 - End Point Control 1 */
-	u32	epctrl2;	/* 0x1c8 - End Point Control 2 */
-	u32	epctrl3;	/* 0x1cc - End Point Control 3 */
-	u32	epctrl4;	/* 0x1d0 - End Point Control 4 */
-	u32	epctrl5;	/* 0x1d4 - End Point Control 5 */
+	u32	epsetupstat;	/* 0x1ac - Endpoint Setup Status */
+	u32	epprime;	/* 0x1b0 - Endpoint Init Status */
+	u32	epflush;	/* 0x1b4 - Endpoint De-initlialize */
+	u32	epstatus;	/* 0x1b8 - Endpoint Status */
+	u32	epcomplete;	/* 0x1bc - Endpoint Complete */
+	u32	epctrl0;	/* 0x1c0 - Endpoint Control 0 */
+	u32	epctrl1;	/* 0x1c4 - Endpoint Control 1 */
+	u32	epctrl2;	/* 0x1c8 - Endpoint Control 2 */
+	u32	epctrl3;	/* 0x1cc - Endpoint Control 3 */
+	u32	epctrl4;	/* 0x1d0 - Endpoint Control 4 */
+	u32	epctrl5;	/* 0x1d4 - Endpoint Control 5 */
 	u8	res9[0x228];
 	u32	snoop1;		/* 0x400 - Snoop 1 */
 	u32	snoop2;		/* 0x404 - Snoop 2 */