diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2015-11-12 19:13:00 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-09 15:03:29 +0100 |
| commit | f2dea5a91615e5da0fd3c6e50029525e6627e215 (patch) | |
| tree | 27a77c5afe2b8447c9a827d68e04afe72d337ac8 | |
| parent | 4fdfb92d7922ce5117fb1f631712939afafbf9fa (diff) | |
colibri_imx7.c: adapt ENET1
Output 50MHz reference clock works, sending works but no reception.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | board/toradex/colibri_imx7/colibri_imx7.c | 27 |
1 files changed, 14 insertions, 13 deletions
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 262b0538af7..7c12a5af48f 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -17,6 +17,7 @@ #include <common.h> #include <fsl_esdhc.h> #include <mmc.h> +#include <micrel.h> #include <miiphy.h> #include <netdev.h> #include <power/pmic.h> @@ -43,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) -#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_32OHM) #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) @@ -296,20 +297,17 @@ int board_video_skip(void) #ifdef CONFIG_FEC_MXC static iomux_v3_cfg_t const fec1_pads[] = { - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_CRS__ENET1_CRS | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), /* ENET_RX_EN !!!!!*/ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), +// MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), - MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), }; static void setup_iomux_fec(void) @@ -467,12 +465,13 @@ static int setup_fec(void) = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; int ret; - /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + /* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] + * and output it on the pin */ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], - (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | - IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); - ret = set_clk_enet(ENET_125MHz); + ret = set_clk_enet(ENET_50MHz); if (ret) return ret; @@ -482,11 +481,13 @@ static int setup_fec(void) int board_phy_config(struct phy_device *phydev) { +#if 0 /* enable rgmii rxc skew and phy mode select to RGMII copper */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21); phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7); +#endif if (phydev->drv->config) phydev->drv->config(phydev); |