x86: Remove HAVE_ACPI_RESUME

These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

6 files changed, 0 insertions, 44 deletions

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 03874448a61..343bfb4e98e 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -298,16 +298,7 @@ int print_cpuinfo(void)
 	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
 
 	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		debug("Resume from S3 detected.\n");
-		boot_mode = PEI_BOOT_RESUME;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-#else
 		debug("Resume from S3 detected, but disabled.\n");
-#endif
 	} else {
 		/*
 		 * TODO: An indication of life might be possible here (e.g.
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 3efd3e841f4..af5d4a89089 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -240,15 +240,6 @@ static void pch_rtc_init(pci_dev_t dev)
 	}
 	debug("rtc_failed = 0x%x\n", rtc_failed);
 
-#if CONFIG_HAVE_ACPI_RESUME
-	/* Avoid clearing pending interrupts and resetting the RTC control
-	 * register in the resume path because the Linux kernel relies on
-	 * this to know if it should restart the RTC timerqueue if the wake
-	 * was due to the RTC alarm.
-	 */
-	if (acpi_get_slp_type() == 3)
-		return;
-#endif
 	/* TODO: Handle power failure */
 	if (rtc_failed)
 		printf("RTC power failed\n");
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index e95e60e5190..e3d8c139dfd 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -169,20 +169,4 @@ void northbridge_init(pci_dev_t dev)
 
 void northbridge_enable(pci_dev_t dev)
 {
-#if CONFIG_HAVE_ACPI_RESUME
-	switch (x86_pci_read_config32(dev, SKPAD)) {
-	case 0xcafebabe:
-		debug("Normal boot.\n");
-		apci_set_slp_type(0);
-		break;
-	case 0xcafed00d:
-		debug("S3 Resume.\n");
-		apci_set_slp_type(3);
-		break;
-	default:
-		debug("Unknown boot method, assuming normal.\n");
-		apci_set_slp_type(0);
-		break;
-	}
-#endif
 }
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index ce976db8b0f..6b139392b56 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
-	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_8192
 
 config PCIE_ECAM_BASE
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index c1cf89cbebe..ae96d23d030 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select X86_RESET_VECTOR
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
-	select HAVE_ACPI_RESUME
 	select BOARD_ROMSIZE_KB_8192
 
 config SYS_CAR_ADDR
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index d2445438a6c..ad1167e2b65 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -33,10 +33,6 @@
 #include <video_fb.h>
 #include <linux/screen_info.h>
 
-#ifdef CONFIG_HAVE_ACPI_RESUME
-#include <asm/acpi.h>
-#endif
-
 __weak bool board_should_run_oprom(pci_dev_t dev)
 {
 	return true;
@@ -44,10 +40,6 @@ __weak bool board_should_run_oprom(pci_dev_t dev)
 
 static bool should_load_oprom(pci_dev_t dev)
 {
-#ifdef CONFIG_HAVE_ACPI_RESUME
-	if (acpi_get_slp_type() == 3)
-		return false;
-#endif
 	if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM))
 		return 1;
 	if (board_should_run_oprom(dev))