powerpc: ppc4xx: remove board support for bluestone

This board has been orphaned for more than 6 months.

It is the last board defining CONFIG_APM821XX.
The code inside #ifdef CONFIG_APM821XX should be removed too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

20 files changed, 19 insertions, 540 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index d525ad3bd64..56abe8dc56f 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -52,9 +52,6 @@ config TARGET_ACADIA
 config TARGET_BAMBOO
 	bool "Support bamboo"
 
-config TARGET_BLUESTONE
-	bool "Support bluestone"
-
 config TARGET_BUBINGA
 	bool "Support bubinga"
 
@@ -239,7 +236,6 @@ endchoice
 
 source "board/amcc/acadia/Kconfig"
 source "board/amcc/bamboo/Kconfig"
-source "board/amcc/bluestone/Kconfig"
 source "board/amcc/bubinga/Kconfig"
 source "board/amcc/canyonlands/Kconfig"
 source "board/amcc/ebony/Kconfig"
diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c
index 6a485264e7c..aab65d405c5 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu.c
@@ -234,20 +234,6 @@ static char *bootstrap_str[] = {
 };
 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 #endif
-#if defined(CONFIG_APM821XX)
-#define SDR0_PINSTP_SHIFT       29
-static char *bootstrap_str[] = {
-	"RESERVED",
-	"RESERVED",
-	"RESERVED",
-	"NAND (8 bits)",
-	"NOR  (8 bits)",
-	"NOR  (8 bits) w/PLL Bypassed",
-	"I2C (Addr 0x54)",
-	"I2C (Addr 0x52)",
-};
-static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
-#endif
 
 #if defined(SDR0_PINSTP_SHIFT)
 static int bootstrap_option(void)
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 0b27d2912d1..22561231cb8 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -284,7 +284,7 @@ cpu_init_f (void)
 	reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
 
 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
-    !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE)
+    !defined(CONFIG_SYS_4xx_GPIO_TABLE)
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
@@ -440,7 +440,7 @@ cpu_init_f (void)
 #if defined(CONFIG_405EX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c
index 4baee7774c5..3e1a7016d94 100644
--- a/arch/powerpc/cpu/ppc4xx/speed.c
+++ b/arch/powerpc/cpu/ppc4xx/speed.c
@@ -171,7 +171,7 @@ ulong get_PCI_freq (void)
 #elif defined(CONFIG_440)
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 static u8 pll_fwdv_multi_bits[] = {
 	/* values for:  1 - 16 */
 	0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
@@ -232,78 +232,6 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv)
 	return 0;
 }
 
-#if defined(CONFIG_APM821XX)
-
-void get_sys_info(sys_info_t *sysInfo)
-{
-	unsigned long plld;
-	unsigned long temp;
-	unsigned long mul;
-	unsigned long cpudv;
-	unsigned long plb2dv;
-	unsigned long ddr2dv;
-
-	/* Calculate Forward divisor A and Feeback divisor */
-	mfcpr(CPR0_PLLD, plld);
-
-	temp = CPR0_PLLD_FWDVA(plld);
-	sysInfo->pllFwdDivA = get_cpr0_fwdv(temp);
-
-	temp = CPR0_PLLD_FDV(plld);
-	sysInfo->pllFbkDiv = get_cpr0_fbdv(temp);
-
-	/* Calculate OPB clock divisor */
-	mfcpr(CPR0_OPBD, temp);
-	temp = CPR0_OPBD_OPBDV(temp);
-	sysInfo->pllOpbDiv = temp ? temp : 4;
-
-	/* Calculate Peripheral clock divisor */
-	mfcpr(CPR0_PERD, temp);
-	temp = CPR0_PERD_PERDV(temp);
-	sysInfo->pllExtBusDiv = temp ? temp : 4;
-
-	/* Calculate CPU clock divisor */
-	mfcpr(CPR0_CPUD, temp);
-	temp = CPR0_CPUD_CPUDV(temp);
-	cpudv = temp ? temp : 8;
-
-	/* Calculate PLB2 clock divisor */
-	mfcpr(CPR0_PLB2D, temp);
-	temp = CPR0_PLB2D_PLB2DV(temp);
-	plb2dv = temp ? temp : 4;
-
-	/* Calculate DDR2 clock divisor */
-	mfcpr(CPR0_DDR2D, temp);
-	temp = CPR0_DDR2D_DDR2DV(temp);
-	ddr2dv = temp ? temp : 4;
-
-	/* Calculate 'M' based on feedback source */
-	mfcpr(CPR0_PLLC, temp);
-	temp = CPR0_PLLC_SEL(temp);
-	if (temp == 0) {
-		/* PLL internal feedback */
-		mul = sysInfo->pllFbkDiv;
-	} else {
-		/* PLL PerClk feedback */
-		mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv
-			* plb2dv * 2 * sysInfo->pllOpbDiv *
-			  sysInfo->pllExtBusDiv;
-	}
-
-	/* Now calculate the individual clocks */
-	sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1);
-	sysInfo->freqProcessor = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv;
-	sysInfo->freqPLB = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv / plb2dv / 2;
-	sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv;
-	sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv;
-	sysInfo->freqDDR = sysInfo->freqVCOMhz /
-		sysInfo->pllFwdDivA / cpudv / ddr2dv / 2;
-	sysInfo->freqUART = sysInfo->freqPLB;
-}
-
-#else
 /*
  * AMCC_TODO: verify this routine against latest EAS, cause stuff changed
  *            with latest EAS
@@ -361,7 +289,6 @@ void get_sys_info (sys_info_t * sysInfo)
 
 	return;
 }
-#endif
 
 #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 11b55d5a56e..09a02d771c2 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -664,8 +664,7 @@ _start:
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
 	mtdcr	L2_CACHE_CFG,r0		/* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-      defined(CONFIG_APM821XX)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	lis	r1, 0x0000
 	ori	r1,r1,0x0008		/* Set L2_CACHE_CFG[RDBW]=1 */
 	mtdcr	L2_CACHE_CFG,r1
@@ -694,7 +693,7 @@ _start:
 	ori	r1,r1, 0x0980		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
-      defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
+      defined(CONFIG_460GT)
 	lis	r1,0x0000		/* BAS = X_0000_0000 */
 	ori	r1,r1,0x0984		/* first 64k */
 	mtdcr	ISRAM0_SB0CR,r1
@@ -707,8 +706,7 @@ _start:
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
 	mtdcr	ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	lis	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,ISRAM1_DPC
diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h
deleted file mode 100644
index d027866d3d9..00000000000
--- a/arch/powerpc/include/asm/apm821xx.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _APM821XX_H_
-#define _APM821XX_H_
-
-#define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
-
-/* Memory mapped registers */
-#define CONFIG_SYS_PERIPHERAL_BASE	0xEF600000
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
-
-#define GPIO0_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
-
-#define SDR0_SRST0_DMC		0x00200000
-#define SDR0_SRST1_AHB		0x00000040      /* PLB4XAHB bridge */
-
-/* AHB config. */
-#define AHB_TOP			0xA4
-#define AHB_BOT			0xA5
-
-/* clk divisors */
-#define PLLSYS0_FWD_DIV_A_MASK	0x000000f0	/* Fwd Div A */
-#define PLLSYS0_FWD_DIV_B_MASK	0x0000000f	/* Fwd Div B */
-#define PLLSYS0_FB_DIV_MASK	0x0000ff00	/* Feedback divisor */
-#define PLLSYS0_OPB_DIV_MASK	0x0c000000	/* OPB Divisor */
-#define PLLSYS0_EPB_DIV_MASK	0x00000300      /* EPB divisor */
-#define PLLSYS0_EXTSL_MASK	0x00000080      /* PerClk feedback path */
-#define PLLSYS0_PLBEDV0_DIV_MASK	0xe0000000/* PLB Early Clk Div*/
-#define PLLSYS0_PERCLK_DIV_MASK	0x03000000	/* Peripheral Clk Divisor */
-#define PLLSYS0_SEL_MASK	0x18000000	/* 0 = PLL, 1 = PerClk */
-
-/*
-   + * Clocking Controller
-   + */
-#define CPR0_CLKUPD	0x0020
-#define CPR0_PLLC	0x0040
-#define CPR0_PLLC_SEL(pllc)		(((pllc) & 0x01000000) >> 24)
-#define CPR0_PLLD	0x0060
-#define CPR0_PLLD_FDV(plld)		(((plld) & 0xff000000) >> 24)
-#define CPR0_PLLD_FWDVA(plld)		(((plld) & 0x000f0000) >> 16)
-#define CPR0_CPUD	0x0080
-#define CPR0_CPUD_CPUDV(cpud)		(((cpud) & 0x07000000) >> 24)
-#define CPR0_PLB2D	0x00a0
-#define CPR0_PLB2D_PLB2DV(plb2d)	(((plb2d) & 0x06000000) >> 25)
-#define CPR0_OPBD	0x00c0
-#define CPR0_OPBD_OPBDV(opbd)		(((opbd) & 0x03000000) >> 24)
-#define CPR0_PERD	0x00e0
-#define CPR0_PERD_PERDV(perd)		(((perd) & 0x03000000) >> 24)
-#define CPR0_DDR2D	0x0100
-#define CPR0_DDR2D_DDR2DV(ddr2d) 	(((ddr2d) & 0x06000000) >> 25)
-#define CLK_ICFG	0x0140
-
-#endif /* _APM821XX_H_ */
diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h
index 07a3fe033fc..952783f9619 100644
--- a/arch/powerpc/include/asm/ppc4xx-ebc.h
+++ b/arch/powerpc/include/asm/ppc4xx-ebc.h
@@ -53,8 +53,7 @@
 #define EBC_NUM_BANKS	6
 #endif
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define EBC_NUM_BANKS	3
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h
index 4d1106b1242..2ae399f2488 100644
--- a/arch/powerpc/include/asm/ppc4xx-isram.h
+++ b/arch/powerpc/include/asm/ppc4xx-isram.h
@@ -8,8 +8,7 @@
 /*
  * Internal SRAM
  */
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ISRAM0_DCR_BASE 0x380
 #else
 #define ISRAM0_DCR_BASE 0x020
@@ -26,8 +25,7 @@
 #define ISRAM0_REVID	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
 #define ISRAM0_DPC	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define ISRAM1_DCR_BASE 0x0B0
 #define ISRAM1_SB0CR	(ISRAM1_DCR_BASE+0x00)	/* SRAM1 bank config 0*/
 #define ISRAM1_BEAR	(ISRAM1_DCR_BASE+0x04)	/* SRAM1 bus error addr reg */
@@ -41,8 +39,6 @@
 
 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define ISRAM1_SIZE 0x0984 /* OCM size 64k */
-#elif defined(CONFIG_APM821XX)
-#define ISRAM1_SIZE 0x0784 /* OCM size 32k */
 #endif
 
 /*
@@ -51,7 +47,7 @@
 #if defined (CONFIG_440GX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define L2_CACHE_BASE	0x030
 #define L2_CACHE_CFG	(L2_CACHE_BASE+0x00)	/* L2 Cache Config      */
 #define L2_CACHE_CMD	(L2_CACHE_BASE+0x01)	/* L2 Cache Command     */
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 12d6d038c7b..e6fed83bf1c 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -276,7 +276,7 @@
  */
 #if defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/
 #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
 #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2)
@@ -349,7 +349,7 @@
 /*
  * Memory controller registers
  */
-#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if defined(CONFIG_405EX)
 #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */
 #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */
 #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */
@@ -359,9 +359,9 @@
 #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */
 #define SDRAM_PUABA	0x09	/* PLB upper address base                    */
 #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */
-#else /* CONFIG_405EX || CONFIG_APM821XX */
+#else /* CONFIG_405EX */
 #define SDRAM_MCSTAT	0x14	/* memory controller status                  */
-#endif /* CONFIG_405EX || CONFIG_APM821XX */
+#endif /* CONFIG_405EX */
 #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */
 #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */
 #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */
@@ -407,12 +407,12 @@
 #define SDRAM_MEMODE	0x89	/* memory extended mode                      */
 #define SDRAM_ECCES	0x98	/* ECC error status                          */
 #define SDRAM_CID	0xA4	/* core ID                                   */
-#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)
+#if !defined(CONFIG_405EX)
 #define SDRAM_RID	0xA8	/* revision ID                               */
 #endif
 #define SDRAM_FCSR	0xB0	/* feedback calibration status               */
 #define SDRAM_RTSR	0xB1	/* run time status tracking                  */
-#if  defined(CONFIG_405EX) || defined(CONFIG_APM821XX)
+#if  defined(CONFIG_405EX)
 #define SDRAM_RID	0xF8	/* revision ID                               */
 #endif
 
diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h
index 05b4690a5c1..58e65c1336f 100644
--- a/arch/powerpc/include/asm/ppc4xx-uic.h
+++ b/arch/powerpc/include/asm/ppc4xx-uic.h
@@ -15,7 +15,7 @@
  */
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)
+    defined(CONFIG_460SX)
 #define UIC_MAX		4
 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_405EX)
@@ -236,8 +236,7 @@
 #define VECNUM_ETH0		(32 + 28)
 #endif /* CONFIG_440SPE */
 
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_APM821XX)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 /* UIC 0 */
 #define VECNUM_UIC2NCI		10
 #define VECNUM_UIC2CI		11
diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h
index e6a3bff079e..b8b0ff9f25b 100644
--- a/arch/powerpc/include/asm/ppc4xx.h
+++ b/arch/powerpc/include/asm/ppc4xx.h
@@ -56,10 +56,6 @@
 #include <asm/ppc460sx.h>
 #endif
 
-#if defined(CONFIG_APM821XX)
-#include <asm/apm821xx.h>
-#endif
-
 /*
  * Common registers for all SoC's
  */
diff --git a/board/amcc/bluestone/Kconfig b/board/amcc/bluestone/Kconfig
deleted file mode 100644
index 255e0137774..00000000000
--- a/board/amcc/bluestone/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_BLUESTONE
-
-config SYS_BOARD
-	default "bluestone"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "bluestone"
-
-endif
diff --git a/board/amcc/bluestone/MAINTAINERS b/board/amcc/bluestone/MAINTAINERS
deleted file mode 100644
index 9eb9bbd01ba..00000000000
--- a/board/amcc/bluestone/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BLUESTONE BOARD
-#M:	Tirumala Marri <tmarri@apm.com>
-S:	Orphan (since 2014-03)
-F:	board/amcc/bluestone/
-F:	include/configs/bluestone.h
-F:	configs/bluestone_defconfig
diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile
deleted file mode 100644
index 07320ce4258..00000000000
--- a/board/amcc/bluestone/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bluestone.o
-extra-y	+= init.o
diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c
deleted file mode 100644
index 6520f75c68b..00000000000
--- a/board/amcc/bluestone/bluestone.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Bluestone board support
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/apm821xx.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * UART0: 2 pins
-	 */
-	mtsdr(SDR0_PFC1, 0x0000000);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: Bluestone Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	return 0;
-}
diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk
deleted file mode 100644
index a947e82af79..00000000000
--- a/board/amcc/bluestone/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2010, Applied Micro Circuits Corporation
-# Author: Tirumala R Marri <tmarri@apm.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# Applied Micro APM821XX Evaluation board.
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S
deleted file mode 100644
index cf22ca63402..00000000000
--- a/board/amcc/bluestone/init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/* TLB 0 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-	4, AC_RWX | SA_G)
-
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
-			0, AC_RWX | SA_G)
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
-			AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
-			CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
-	tlbtab_end
diff --git a/configs/bluestone_defconfig b/configs/bluestone_defconfig
deleted file mode 100644
index 8f83a4308ee..00000000000
--- a/configs/bluestone_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_BLUESTONE=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 48e94ab0aa8..036bc838abd 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+bluestone        powerpc     ppc4xx         -           -           Tirumala Marri <tmarri@apm.com>
 CRAYL1           powerpc     ppc4xx         -           -           David Updegraff <dave@cray.com>
 KAREF            powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
 METROBOX         powerpc     ppc4xx         -           -           Travis Sawyer <travis.sawyer@sandburst.com>
diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h
deleted file mode 100644
index 8bd71c6a154..00000000000
--- a/include/configs/bluestone.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * bluestone.h - configuration for Bluestone (APM821XX)
- *
- * Copyright (c) 2010, Applied Micro Circuits Corporation
- * Author: Tirumala R Marri <tmarri@apm.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_APM821XX		1	/* APM821XX series    */
-#define CONFIG_HOSTNAME		bluestone
-
-#define CONFIG_440		1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
-#endif
-
-/*
- * Include common defines/options for all AMCC eval boards
- */
-#include "amcc-common.h"
-#define CONFIG_SYS_CLK_FREQ	50000000
-
-#define CONFIG_BOARD_TYPES		1	/* support board types */
-#define CONFIG_BOARD_EARLY_INIT_F	1       /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R		1       /* Call misc_init_r */
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-/* EBC stuff */
-/* later mapped to this addr */
-#define CONFIG_SYS_FLASH_BASE		0xFFF00000
-#define CONFIG_SYS_FLASH_SIZE		(4 << 20)	/* 1MB usable */
-
-/* EBC Boot Space: 0xFF000000 */
-#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000
-#define CONFIG_SYS_OCM_BASE		0xE3000000 /* OCM: 32k             */
-#define CONFIG_SYS_SRAM_BASE		0xE8000000 /* SRAM: 256k           */
-#define CONFIG_SYS_AHB_BASE		0xE2000000 /* internal AHB peripherals*/
-
-#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
-/*
- * Initial RAM & stack pointer (placed in OCM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM    */
-#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET	\
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Environment
- */
-/*
- * Define here the location of the environment variables (FLASH).
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI	/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-/* max number of sectors on one chip    */
-#define CONFIG_SYS_MAX_FLASH_SECT	80
-/* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
-/* Timeout for Flash Write (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500
-/* use buffered writes (20x faster)     */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
-/* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector  */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector   */
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-/* SDRAM */
-#define CONFIG_SPD_EEPROM	1       /* Use SPD EEPROM for setup     */
-#define SPD_EEPROM_ADDRESS	{0x53, 0x51}	/* SPD i2c spd addresses */
-#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
-#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
-#define CONFIG_DDR_ECC		1	/* with ECC support             */
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* Data sheet */
-
-/* I2C bootstrap EEPROM */
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
-#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
-#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
-
-/*
- * Ethernet
- */
-#define CONFIG_IBM_EMAC4_V4	1
-#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_NONE_RGMII
-#define CONFIG_HAS_ETH0
-/* PHY address, See schematics  */
-#define CONFIG_PHY_ADDR			0x1f
-/* reset phy upon startup       */
-#define CONFIG_PHY_RESET		1
-/* Include GbE speed/duplex detection */
-#define CONFIG_PHY_GIGE			1
-#define CONFIG_PHY_DYNAMIC_ANEG		1
-
-/*
- * External Bus Controller (EBC) Setup
- **/
-#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_LOCK    |	\
-				 EBC_CFG_PTD_ENABLE   |	\
-				 EBC_CFG_RTC_2048PERCLK | \
-				 EBC_CFG_ATC_HI | \
-				 EBC_CFG_DTC_HI | \
-				 EBC_CFG_CTC_HI | \
-				 EBC_CFG_OEO_PREVIOUS)
-/* NOR Flash */
-#define CONFIG_SYS_EBC_PB0AP 	(EBC_BXAP_BME_DISABLED   | \
-				EBC_BXAP_TWT_ENCODE(64)  | \
-				EBC_BXAP_BCE_DISABLE    | \
-				EBC_BXAP_BCT_2TRANS     | \
-				EBC_BXAP_CSN_ENCODE(1)  | \
-				EBC_BXAP_OEN_ENCODE(2)  | \
-				EBC_BXAP_WBN_ENCODE(2)  | \
-				EBC_BXAP_WBF_ENCODE(2)  | \
-				EBC_BXAP_TH_ENCODE(7)   | \
-				EBC_BXAP_SOR_DELAYED    | \
-				EBC_BXAP_BEM_WRITEONLY  | \
-				EBC_BXAP_PEN_DISABLED)
-/* Peripheral Bank Configuration Register - EBC_BxCR */
-#define CONFIG_SYS_EBC_PB0CR	\
-			(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
-			EBC_BXCR_BS_1MB                | \
-			EBC_BXCR_BU_RW                  | \
-			EBC_BXCR_BW_8BIT)
-
-
-#endif /* __CONFIG_H */