diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-03-30 16:39:53 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-03-30 16:41:57 +0200 |
| commit | f1b985f2d724ccaa4d3def07917f0caaf18fa77d (patch) | |
| tree | f36631cb970052c4c83bbb5c9aebea98c17c47e1 | |
| parent | 480ed1dea103a1c8f4591afc77d2de3c7868d983 (diff) | |
use correct at91rm9200 register name in m501sk board
This fixes a naming bug for at91rm9200 lowlevel init code:
NOR boot flash is on chipselect 0, not chipselect 2. This
makes code use the register name from chip datasheets.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| -rw-r--r-- | board/m501sk/memsetup.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S index 9e174b5b8fc..6aea723f91f 100644 --- a/board/m501sk/memsetup.S +++ b/board/m501sk/memsetup.S @@ -52,8 +52,8 @@ #define MC_AASR_VAL 0x00000000 #define EBI_CFGR 0xFFFFFF64 #define EBI_CFGR_VAL 0x00000000 -#define SMC2_CSR 0xFFFFFF70 -#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC_CSR0 0xFFFFFF70 +#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR 0xFFFFFC28 @@ -141,8 +141,8 @@ SMRDATA: .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL - .word SMC2_CSR - .word SMC2_CSR_VAL + .word SMC_CSR0 + .word SMC_CSR0_VAL .word PLLAR .word PLLAR_VAL .word PLLBR |