diff options
| author | Piotr Wilczek <p.wilczek@samsung.com> | 2013-11-21 15:46:44 +0100 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-12-02 11:22:32 +0900 |
| commit | 4498cf252bfd7f69a4e9aedd897306211a0be5af (patch) | |
| tree | db83f90efbec3c283f8d8c909f2c9a21c1e81a0a | |
| parent | 31e0bd6974cbaca15e15f400acf1d7499e86fe17 (diff) | |
driver:usb:s3c_udc: add support for Exynos4x12
This patch add new defines for usb phy for Exynos4x12.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| -rw-r--r-- | drivers/usb/gadget/regs-otg.h | 5 | ||||
| -rw-r--r-- | drivers/usb/gadget/s3c_udc_otg.c | 9 |
2 files changed, 12 insertions, 2 deletions
diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h index 84bfcc5a01d..ac5d11213de 100644 --- a/drivers/usb/gadget/regs-otg.h +++ b/drivers/usb/gadget/regs-otg.h @@ -226,6 +226,11 @@ struct s3c_usbotg_reg { #define CLK_SEL_12MHZ (0x2 << 0) #define CLK_SEL_48MHZ (0x0 << 0) +#define EXYNOS4X12_ID_PULLUP0 (0x01 << 3) +#define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4) +#define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) +#define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) + /* Device Configuration Register DCFG */ #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) #define DEV_SPEED_FULL_SPEED_20 (0x1 << 0) diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index 7e2020915e0..ba17a04265e 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -167,8 +167,13 @@ void otg_phy_init(struct s3c_udc *dev) writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) &~FORCE_SUSPEND_0), &phy->phypwr); - writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) | - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ + if (s5p_cpu_id == 0x4412) + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | + EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, + &phy->phyclk); /* PLL 24Mhz */ + else + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | + CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) | PHY_SW_RST0, &phy->rstcon); |