Add support for AMCC Sequoia PPC440EPx eval board

- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
  in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
  please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
  in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006

48 files changed, 3606 insertions, 321 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 3c42d93fe84..576cd7fb861 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,16 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add support for AMCC Sequoia PPC440EPx eval board
+  - Add support for PPC440EPx & PPC440GRx
+  - Add support for PPC440EP(x)/GR(x) NAND controller
+    in cpu/ppc4xx directory
+  - Add NAND boot functionality for Sequoia board,
+    please see doc/README.nand-boot-ppc440 for details
+  - This Sequoia NAND image doesn't support environment
+    in NAND for now. This will be added in a short while.
+  Patch by Stefan Roese, 07 Sep 2006
+
 * Fix mkimage -l bug with multifile images on 64bit platforms
   Patch by David Updegraff, 06 Sep 2006
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c4cfb43cf4..42627196f86 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -285,6 +285,7 @@ Stefan Roese <sr@denx.de>
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
+	sequoia			PPC440EPx
 	sycamore		PPC405GPr
 	walnut			PPC405GP
 	yellowstone		PPC440GR
diff --git a/MAKEALL b/MAKEALL
index d2f86d3ac8a..8039f3d7082 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -13,7 +13,7 @@ if [ "${MAKEALL_LOGDIR}" ] ; then
 else
 	LOG_DIR="LOG"
 fi
-	
+
 if [ ! "${BUILD_DIR}" ] ; then
 	BUILD_DIR="."
 fi
@@ -85,9 +85,10 @@ LIST_4xx="	\
 	ML2		ml300		ocotea		OCRTC		\
 	ORSG		p3p440		PCI405		pcs440ep	\
 	PIP405		PLU405		PMC405		PPChameleonEVB	\
-	sbc405		VOH405		VOM405		W7OLMC		\
-	W7OLMG		walnut		WUH405		XPEDITE1K	\
-	yellowstone	yosemite	yucca		bamboo		\
+	sbc405		sequoia		sequoia_nand	VOH405		\
+	VOM405		W7OLMC		W7OLMG		walnut		\
+	WUH405		XPEDITE1K	yellowstone	yosemite	\
+	yucca		bamboo		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index fc7b117e3fe..a63aaef15bc 100644
--- a/Makefile
+++ b/Makefile
@@ -48,7 +48,7 @@ VENDOR=
 #
 # U-boot build supports producing a object files to the separate external
 # directory. Two use cases are supported:
-# 
+#
 # 1) Add O= to the make command line
 # 'make O=/tmp/build all'
 #
@@ -59,12 +59,12 @@ VENDOR=
 # The second approach can also be used with a MAKEALL script
 # 'export BUILD_DIR=/tmp/build'
 # './MAKEALL'
-# 
+#
 # Command line 'O=' setting overrides BUILD_DIR environent variable.
-# 
+#
 # When none of the above methods is used the local build is performed and
 # the object files are placed in the source directory.
-# 
+#
 
 ifdef O
 ifeq ("$(origin O)", "command line")
@@ -101,7 +101,7 @@ src := $(SRCTREE)/
 else
 obj :=
 src :=
-endif   
+endif
 export obj src
 
 #########################################################################
@@ -214,13 +214,18 @@ SUBDIRS	= tools \
 	  post/cpu
 .PHONY : $(SUBDIRS)
 
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+NAND_SPL = nand_spl
+U_BOOT_NAND = $(obj)u-boot-nand.bin
+endif
+
 __OBJS := $(subst $(obj),,$(OBJS))
 __LIBS := $(subst $(obj),,$(LIBS))
 
 #########################################################################
 #########################################################################
 
-ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND)
 
 all:		$(ALL)
 
@@ -258,6 +263,12 @@ $(LIBS):
 $(SUBDIRS):
 		$(MAKE) -C $@ all
 
+$(NAND_SPL):	version
+		$(MAKE) -C nand_spl all
+
+$(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin
+		cat nand_spl/u-boot-spl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
+
 version:
 		@echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
 		echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
@@ -309,7 +320,8 @@ endif
 #########################################################################
 
 unconfig:
-	@rm -f $(obj)include/config.h $(obj)include/config.mk $(obj)board/*/config.tmp
+	@rm -f $(obj)include/config.h $(obj)include/config.mk \
+		$(obj)board/*/config.tmp $(obj)board/*/*/config.tmp
 
 #========================================================================
 # PowerPC
@@ -1128,6 +1140,17 @@ PPChameleonEVB_HI_33_config:	unconfig
 sbc405_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
 
+sequoia_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx sequoia amcc
+
+sequoia_nand_config:	unconfig
+	@ln -s board/amcc/sequoia/Makefile nand_spl/Makefile
+	@echo "#define CONFIG_NAND_U_BOOT" >include/config.h
+	@echo "Compile NAND boot image for sequoia"
+	@$(MKCONFIG) -a sequoia ppc ppc4xx sequoia amcc
+	@echo "TEXT_BASE = 0x01000000" >board/amcc/sequoia/config.tmp
+	@echo "CONFIG_NAND_U_BOOT = y" >> include/config.mk
+
 sycamore_config:	unconfig
 	@echo "Configuring for sycamore board as subset of walnut..."
 	@$(MKCONFIG) -a walnut ppc ppc4xx walnut amcc
@@ -2195,6 +2218,8 @@ clean:
 	rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
 	rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
 	rm -f $(obj)include/bmp_logo.h
+	find nand_spl -lname "*" -print | xargs rm -f
+	rm -f nand_spl/u-boot-spl nand_spl/u-boot-spl.map
 
 clobber:	clean
 	find $(OBJTREE) -type f \( -name .depend \
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
new file mode 100644
index 00000000000..b29c04a0d9e
--- /dev/null
+++ b/board/amcc/sequoia/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/include/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o sdram.o
+SOBJS	= init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
new file mode 100644
index 00000000000..7713a72be85
--- /dev/null
+++ b/board/amcc/sequoia/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
new file mode 100644
index 00000000000..3d4ac8543d5
--- /dev/null
+++ b/board/amcc/sequoia/init.S
@@ -0,0 +1,157 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+#define _256M       0x10000000
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/*
+	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+	 * speed up boot process. It is patched after relocation to enable SA_I
+	*/
+#ifndef CONFIG_NAND_SPL
+	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+#else
+	tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+	/* TLB-entry for DDR SDRAM (Up to 2GB) */
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+#ifdef CFG_INIT_RAM_DCACHE
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+#endif
+
+	/* TLB-entry for PCI Memory */
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+
+	/* TLB-entry for EBC */
+	tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for NAND */
+	tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for Internal Registers & OCM */
+	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+
+	/*TLB-entry PCI registers*/
+	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+
+	/* TLB-entry for peripherals */
+	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	tlbtab_end
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * For NAND booting the first TLB has to be reconfigured to full size
+	 * and with caching disabled after running from RAM!
+	 */
+#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+
+	.globl	reconfig_tlb0
+reconfig_tlb0:
+	sync
+	isync
+	addi	r4,r0,0x0000		/* TLB entry #0 */
+	lis	r5,TLB00@h
+	ori	r5,r5,TLB00@l
+	tlbwe	r5,r4,0x0000		/* Save it out */
+	lis	r5,TLB01@h
+	ori	r5,r5,TLB01@l
+	tlbwe	r5,r4,0x0001		/* Save it out */
+	lis	r5,TLB02@h
+	ori	r5,r5,TLB02@l
+	tlbwe	r5,r4,0x0002		/* Save it out */
+	sync
+	isync
+	blr
+#endif
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
new file mode 100644
index 00000000000..a62648bb5f4
--- /dev/null
+++ b/board/amcc/sequoia/sdram.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	volatile ulong val;
+
+	mtsdram(DDR0_02, 0x00000000);
+
+	/*
+	 * Soft-reset SDRAM controller
+	 */
+	mtsdr(sdr_srst, SDR0_SRST0_DMC);
+	mtsdr(sdr_srst, 0x00000000);
+
+	mtsdram(DDR0_00, 0x0000190A);
+	mtsdram(DDR0_01, 0x01000000);
+	mtsdram(DDR0_03, 0x02030602);
+	mtsdram(DDR0_04, 0x13030300);
+	mtsdram(DDR0_05, 0x0202050E);
+	mtsdram(DDR0_06, 0x0104C823);
+	mtsdram(DDR0_07, 0x000D0100);
+	mtsdram(DDR0_08, 0x02360001);
+	mtsdram(DDR0_09, 0x00011D5F);
+	mtsdram(DDR0_10, 0x00000300);
+	mtsdram(DDR0_11, 0x0027C800);
+	mtsdram(DDR0_12, 0x00000003);
+	mtsdram(DDR0_14, 0x00000000);
+	mtsdram(DDR0_17, 0x19000000);
+	mtsdram(DDR0_18, 0x19191919);
+	mtsdram(DDR0_19, 0x19191919);
+	mtsdram(DDR0_20, 0x0B0B0B0B);
+	mtsdram(DDR0_21, 0x0B0B0B0B);
+	mtsdram(DDR0_22, 0x00267F0B);
+	mtsdram(DDR0_23, 0x00000000);
+	mtsdram(DDR0_24, 0x01010002);
+	mtsdram(DDR0_26, 0x5B260181);
+	mtsdram(DDR0_27, 0x0000682B);
+	mtsdram(DDR0_28, 0x00000000);
+	mtsdram(DDR0_31, 0x00000000);
+	mtsdram(DDR0_42, 0x01000006);
+	mtsdram(DDR0_43, 0x050A0200);
+	mtsdram(DDR0_44, 0x00000005);
+	mtsdram(DDR0_02, 0x00000001);
+
+	/*
+	 * Wait for DCC master delay line to finish calibration
+	 */
+	mfsdram(DDR0_17, val);
+	while (((val >> 8) & 0x000007f) == 0) {
+		mfsdram(DDR0_17, val);
+	}
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+	return (CFG_MBYTES_SDRAM << 20);
+}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
new file mode 100644
index 00000000000..95734b9c57c
--- /dev/null
+++ b/board/amcc/sequoia/sequoia.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "sequoia.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+int board_early_init_f(void)
+{
+	unsigned long sdr0_cust0;
+	unsigned long sdr0_pfc1, sdr0_pfc2;
+	register uint reg;
+
+	mtdcr(ebccfga, xbcfg);
+	mtdcr(ebccfgd, 0xb8400000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/* test-only: take GPIO init from pcs440ep ???? in config file */
+	out32(GPIO0_OR, 0x00000000);
+	out32(GPIO0_TCR, 0x0000000f);
+	out32(GPIO0_OSRL, 0x50015400);
+	out32(GPIO0_OSRH, 0x550050aa);
+	out32(GPIO0_TSRL, 0x50015400);
+	out32(GPIO0_TSRH, 0x55005000);
+	out32(GPIO0_ISR1L, 0x50000000);
+	out32(GPIO0_ISR1H, 0x00000000);
+	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2H, 0x00000100);
+	out32(GPIO0_ISR3L, 0x00000000);
+	out32(GPIO0_ISR3H, 0x00000000);
+
+	out32(GPIO1_OR, 0x00000000);
+	out32(GPIO1_TCR, 0xc2000000);
+	out32(GPIO1_OSRL, 0x5c280000);
+	out32(GPIO1_OSRH, 0x00000000);
+	out32(GPIO1_TSRL, 0x0c000000);
+	out32(GPIO1_TSRH, 0x00000000);
+	out32(GPIO1_ISR1L, 0x00005550);
+	out32(GPIO1_ISR1H, 0x00000000);
+	out32(GPIO1_ISR2L, 0x00050000);
+	out32(GPIO1_ISR2H, 0x00000000);
+	out32(GPIO1_ISR3L, 0x01400000);
+	out32(GPIO1_ISR3H, 0x00000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+	mtdcr(uic2er, 0x00000000);	/* disable all */
+	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
+	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(uic2sr, 0xffffffff);	/* clear all */
+
+	/* 50MHz tmrclk */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+	/* clear write protects */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+	/* enable Ethernet */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
+
+	/* enable USB device */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
+
+	/* select Ethernet pins */
+	mfsdr(SDR0_PFC1, sdr0_pfc1);
+	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
+	mfsdr(SDR0_PFC2, sdr0_pfc2);
+	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
+	mtsdr(SDR0_PFC2, sdr0_pfc2);
+	mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+	/* PCI arbiter enabled */
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);
+
+	/* setup NAND FLASH */
+	mfsdr(SDR0_CUST0, sdr0_cust0);
+        sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
+		SDR0_CUST0_NDFC_ENABLE		|
+		SDR0_CUST0_NDFC_BW_8_BIT	|
+		SDR0_CUST0_NDFC_ARE_MASK	|
+		(0x80000000 >> (28 + CFG_NAND_CS));
+        mtsdr(SDR0_CUST0, sdr0_cust0);
+
+	return 0;
+}
+
+/*---------------------------------------------------------------------------+
+  | misc_init_r.
+  +---------------------------------------------------------------------------*/
+int misc_init_r(void)
+{
+	uint pbcr;
+	int size_val = 0;
+	unsigned long usb2d0cr = 0;
+	unsigned long usb2phy0cr, usb2h0cr = 0;
+	unsigned long sdr0_pfc1;
+	char *act = getenv("usbact");
+
+	/*
+	 * FLASH stuff...
+	 */
+
+	/* Re-do sizing to get full correct info */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(ebccfga, pb3cr);
+#else
+	mtdcr(ebccfga, pb0cr);
+#endif
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+	mtdcr(ebccfga, pb3cr);
+#else
+	mtdcr(ebccfga, pb0cr);
+#endif
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#ifdef CFG_ENV_IS_IN_FLASH
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_ENV_ADDR_REDUND,
+			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+			    &flash_info[0]);
+#endif
+
+	/*
+	 * USB suff...
+	 */
+	if (act == NULL || strcmp(act, "hostdev") == 0)	{
+		/* SDR Setting */
+        	mfsdr(SDR0_PFC1, sdr0_pfc1);
+        	mfsdr(SDR0_USB0, usb2d0cr);
+        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+        	mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+
+		/* An 8-bit/60MHz interface is the only possible alternative
+		   when connecting the Device to the PHY */
+        	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+
+        	/* To enable the USB 2.0 Device function through the UTMI interface */
+        	usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/
+
+        	sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/
+
+        	mtsdr(SDR0_PFC1, sdr0_pfc1);
+        	mtsdr(SDR0_USB0, usb2d0cr);
+        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+		/*clear resets*/
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Host(int phy) Device(ext phy)\n");
+
+	} else if (strcmp(act, "dev") == 0) {
+		/*-------------------PATCH-------------------------------*/
+		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x672c6000);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000080);
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60206000);
+
+		*(unsigned int *)(0xe0000350) = 0x00000001;
+
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x60306000);
+		/*-------------------PATCH-------------------------------*/
+
+		/* SDR Setting */
+        	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mfsdr(SDR0_USB2H0CR, usb2h0cr);
+		mfsdr(SDR0_USB0, usb2d0cr);
+		mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+        	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;	/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		/*0*/
+		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+        	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		/*0*/
+
+		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+        	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		/*0*/
+
+		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+        	usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;		/*0*/
+
+		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+        	sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		/*1*/
+
+        	mtsdr(SDR0_USB2H0CR, usb2h0cr);
+        	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+		mtsdr(SDR0_USB0, usb2d0cr);
+		mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+		/*clear resets*/
+		udelay (1000);
+		mtsdr(SDR0_SRST1, 0x00000000);
+		udelay (1000);
+		mtsdr(SDR0_SRST0, 0x00000000);
+
+		printf("USB:   Device(int phy)\n");
+	}
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_MBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+#if 0
+	/*--------------------------------------------------------------------------+
+	 *	Cactus is always configured as the host & requires the
+	 *	PCI arbiter to be enabled ???
+	 *--------------------------------------------------------------------------*/
+	unsigned long strap;
+	mfsdr(sdr_sdstp1, strap);
+	if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
+		printf("PCI: SDR0_STRP1[PAE] not set.\n");
+		printf("PCI: Configuration aborted.\n");
+		return 0;
+	}
+#endif
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440EPX PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Cactus is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
new file mode 100644
index 00000000000..1d44b164649
--- /dev/null
+++ b/board/amcc/sequoia/sequoia.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*----------------------------------------------------------------------------+
+  | EBC Configuration Register - EBC0_CFG
+  +----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED	    0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK	    0x38000000
+#define EBC0_CFG_RTC_16PERCLK	    0x00000000
+#define EBC0_CFG_RTC_32PERCLK	    0x08000000
+#define EBC0_CFG_RTC_64PERCLK	    0x10000000
+#define EBC0_CFG_RTC_128PERCLK	    0x18000000
+#define EBC0_CFG_RTC_256PERCLK	    0x20000000
+#define EBC0_CFG_RTC_512PERCLK	    0x28000000
+#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
+#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW	    0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
+#define EBC0_CFG_EMPL_HIGH	    0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW	    0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
+#define EBC0_CFG_EMPH_HIGH	    0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW	    0x00000000
+#define EBC0_CFG_BPF_TWODW	    0x00100000
+#define EBC0_CFG_BPF_FOURDW	    0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT	    0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED	    0x00000000
+#define EBC0_CFG_PME_ENABLED	    0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
+
+#define SDR0_USB0                    0x0320     /* USB Control Register */
diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds
new file mode 100644
index 00000000000..c3d3d968fed
--- /dev/null
+++ b/board/amcc/sequoia/u-boot-nand.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds
new file mode 100644
index 00000000000..a423f982858
--- /dev/null
+++ b/board/amcc/sequoia/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 256e4bc7968..70de795deed 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -62,11 +62,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
     defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-	defined(CONFIG_440SP)
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ||	\
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	print_str ("procfreq",	    strmhz(buf, bd->bi_procfreq));
 	print_str ("plb_busfreq",   strmhz(buf, bd->bi_plb_busfreq));
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	print_str ("pci_busfreq",   strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */
diff --git a/config.mk b/config.mk
index 3ed7107fb80..0f5d0f43d94 100644
--- a/config.mk
+++ b/config.mk
@@ -132,8 +132,12 @@ DBGFLAGS= -g # -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
+ifeq ($(CONFIG_NAND_U_BOOT),y)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+else
 LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
 endif
+endif
 OBJCFLAGS += --gap-fill=0xff
 
 gccincdir := $(shell $(CC) -print-file-name=include)
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 0b0686bcf71..03128d3f6d1 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -555,7 +555,8 @@ void pci_440_init (struct pci_controller *hose)
 #ifdef CONFIG_PCI_SCAN_SHOW
 		printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
-#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 #endif
 		hose->last_busno = pci_hose_scan(hose);
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index fab65aff78a..5b1c17c351a 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -130,7 +130,17 @@
 #define BI_PHYMODE_NONE	 0
 #define BI_PHYMODE_ZMII	 1
 #define BI_PHYMODE_RGMII 2
+#define BI_PHYMODE_GMII  3
+#define BI_PHYMODE_RTBI  4
+#define BI_PHYMODE_TBI   5
+#if defined (CONFIG_440EPX)
+#define BI_PHYMODE_SMII  6
+#define BI_PHYMODE_MII   7
+#endif
 
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_MFR_ETH_CLK_SEL_V(n)	((0x01<<27) / (n+1))
+#endif
 
 /*-----------------------------------------------------------------------------+
  * Global variables. TX and RX descriptors and buffers.
@@ -181,7 +191,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 {
 	EMAC_4XX_HW_PST hw_p = dev->priv;
 	uint32_t failsafe = 10000;
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned long mfr;
 #endif
 
@@ -205,19 +215,19 @@ static void ppc_4xx_eth_halt (struct eth_device *dev)
 	}
 
 	/* EMAC RESET */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr |= 0x08000000;
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
 	out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr &= ~0x08000000;
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
@@ -317,10 +327,50 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
 	out32 (RGMII_FER, rmiifer);
 
 	return ((int)pfc1);
-
 }
 #endif	/* CONFIG_440_GX */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
+{
+	unsigned long zmiifer=0x0;
+
+	/*
+	 * Right now only 2*RGMII is supported. Please extend when needed.
+	 * sr - 2006-08-29
+	 */
+	switch (1) {
+	case 0:
+		/* 1 x GMII port */
+		out32 (ZMII_FER, 0x00);
+		out32 (RGMII_FER, 0x00000037);
+		bis->bi_phymode[0] = BI_PHYMODE_GMII;
+		bis->bi_phymode[1] = BI_PHYMODE_NONE;
+		break;
+	case 1:
+		/* 2 x RGMII ports */
+		out32 (ZMII_FER, 0x00);
+		out32 (RGMII_FER, 0x00000055);
+		bis->bi_phymode[0] = BI_PHYMODE_RGMII;
+		bis->bi_phymode[1] = BI_PHYMODE_RGMII;
+		break;
+	case 2:
+		/* 2 x SMII ports */
+
+		break;
+	default:
+		break;
+	}
+
+	/* Ensure we setup mdio for this devnum and ONLY this devnum */
+	zmiifer = in32 (ZMII_FER);
+	zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
+	out32 (ZMII_FER, zmiifer);
+
+	return ((int)0x0);
+}
+#endif	/* CONFIG_440EPX */
+
 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 {
 	int i, j;
@@ -332,13 +382,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	unsigned mode_reg;
 	unsigned short devnum;
 	unsigned short reg_short;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	sys_info_t sysinfo;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	int ethgroup = -1;
 #endif
 #endif
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
 	unsigned long mfr;
 #endif
 
@@ -352,7 +405,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		return -1;
 	}
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* Need to get the OPB frequency so we can access the PHY */
 	get_sys_info (&sysinfo);
 #endif
@@ -407,7 +462,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
-#elif defined(CONFIG_440GX)
+#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
 #elif defined(CONFIG_440GP)
 	/* set RMII mode */
@@ -429,10 +484,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	__asm__ volatile ("eieio");
 
 	/* reset emac so we have access to the phy */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* provide clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr |= 0x08000000;
+	mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
@@ -444,15 +499,19 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 		udelay (1000);
 		failsafe--;
 	}
+	if (failsafe <= 0)
+		printf("\nProblem resetting EMAC!\n");
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	/* remove clocks for EMAC internal loopback  */
 	mfsdr (sdr_mfr, mfr);
-	mfr &= ~0x08000000;
+	mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
 	mtsdr(sdr_mfr, mfr);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	/* Whack the M1 register */
 	mode_reg = 0x0;
 	mode_reg &= ~0x00000038;
@@ -502,15 +561,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	 * otherwise, just check the speeds & feeds
 	 */
 	if (hw_p->first_init == 0) {
+#if defined(CONFIG_88E1111_CLK_DELAY)
+		/*
+		 * On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
+		 * the "RGMII transmit timing control" and "RGMII receive
+		 * timing control" bits set, so that Gbit communication works
+		 * without problems.
+		 * Also set the "Transmitter disable" to 1 to enable the
+		 * transmitter.
+		 * After setting these bits a soft-reset must occur for this
+		 * change to become active.
+		 */
+		miiphy_read (dev->name, reg, 0x14, &reg_short);
+		reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
+		miiphy_write (dev->name, reg, 0x14, reg_short);
+#endif
+#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
+		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
+		miiphy_write (dev->name, reg, 0x18, 0x4101);
+		miiphy_write (dev->name, reg, 0x09, 0x0e00);
+		miiphy_write (dev->name, reg, 0x04, 0x01e1);
+#endif
 		miiphy_reset (dev->name, reg);
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+
 #if defined(CONFIG_CIS8201_PHY)
 		/*
 		 * Cicada 8201 PHY needs to have an extended register whacked
 		 * for RGMII mode.
 		 */
-		if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
+		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
 #if defined(CONFIG_CIS8201_SHORT_ETCH)
 			miiphy_write (dev->name, reg, 23, 0x1300);
 #else
@@ -580,7 +663,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			(int) speed, (duplex == HALF) ? "HALF" : "FULL");
 	}
 
-#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	mfsdr(sdr_mfr, reg);
 	if (speed == 100) {
@@ -603,15 +687,34 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
 		else if (speed == 100)
 			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
-		else
+		else if (speed == 10)
 			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
-
+		else {
+			printf("Error in RGMII Speed\n");
+			return -1;
+		}
 		out32 (RGMII_SSR, reg);
 	}
 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	if (speed == 1000)
+		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
+	else if (speed == 100)
+		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
+	else if (speed == 10)
+		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
+	else {
+		printf("Error in RGMII Speed\n");
+		return -1;
+	}
+	out32 (RGMII_SSR, reg);
+#endif
+
 	/* set the Mal configuration reg */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
 	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
 #else
@@ -795,8 +898,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 
 	/* set speed */
 	if (speed == _1000BASET) {
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		unsigned long pfc1;
+
 		mfsdr (sdr_pfc1, pfc1);
 		pfc1 |= SDR0_PFC1_EM_1000;
 		mtsdr (sdr_pfc1, pfc1);
@@ -942,6 +1047,14 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
 #define UIC0SR		uic0sr
 #endif
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define UICMSR_ETHX	uic0msr
+#define UICSR_ETHX	uic0sr
+#else
+#define UICMSR_ETHX	uic1msr
+#define UICSR_ETHX	uic1sr
+#endif
+
 int enetInt (struct eth_device *dev)
 {
 	int serviced;
@@ -950,6 +1063,7 @@ int enetInt (struct eth_device *dev)
 	unsigned long emac_isr = 0;
 	unsigned long mal_rx_eob;
 	unsigned long my_uic0msr, my_uic1msr;
+	unsigned long my_uicmsr_ethx;
 
 #if defined(CONFIG_440GX)
 	unsigned long my_uic2msr;
@@ -977,8 +1091,11 @@ int enetInt (struct eth_device *dev)
 #if defined(CONFIG_440GX)
 		my_uic2msr = mfdcr (uic2msr);
 #endif
+		my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
+
 		if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
-		    && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+		    && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
+		    && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
 			/* not for us */
 			return (rc);
 		}
@@ -997,8 +1114,7 @@ int enetInt (struct eth_device *dev)
 			mal_isr = mfdcr (malesr);
 			/* look for mal error */
 			if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
-				mal_err (dev, mal_isr, my_uic0msr,
-					 MAL_UIC_DEF, MAL_UIC_ERR);
+				mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
 				serviced = 1;
 				rc = 0;
 			}
@@ -1006,7 +1122,7 @@ int enetInt (struct eth_device *dev)
 
 		/* port by port dispatch of emac interrupts */
 		if (hw_p->devnum == 0) {
-			if (UIC_ETH0 & my_uic1msr) {	/* look for EMAC errors */
+			if (UIC_ETH0 & my_uicmsr_ethx) {	/* look for EMAC errors */
 				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
 				if ((hw_p->emac_ier & emac_isr) != 0) {
 					emac_err (dev, emac_isr);
@@ -1017,14 +1133,15 @@ int enetInt (struct eth_device *dev)
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
 				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
 				return (rc);	/* we had errors so get out */
 			}
 		}
 
 #if !defined(CONFIG_440SP)
 		if (hw_p->devnum == 1) {
-			if (UIC_ETH1 & my_uic1msr) {	/* look for EMAC errors */
+			if (UIC_ETH1 & my_uicmsr_ethx) {	/* look for EMAC errors */
 				emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
 				if ((hw_p->emac_ier & emac_isr) != 0) {
 					emac_err (dev, emac_isr);
@@ -1035,7 +1152,8 @@ int enetInt (struct eth_device *dev)
 			if ((hw_p->emac_ier & emac_isr)
 			    || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
 				mtdcr (UIC0SR, UIC_MRE | UIC_MTE);	/* Clear */
-				mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
+				mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+				mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
 				return (rc);	/* we had errors so get out */
 			}
 		}
@@ -1102,10 +1220,10 @@ int enetInt (struct eth_device *dev)
 		mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE);	/* Clear */
 		switch (hw_p->devnum) {
 		case 0:
-			mtdcr (uic1sr, UIC_ETH0);
+			mtdcr (UICSR_ETHX, UIC_ETH0);
 			break;
 		case 1:
-			mtdcr (uic1sr, UIC_ETH1);
+			mtdcr (UICSR_ETHX, UIC_ETH1);
 			break;
 #if defined (CONFIG_440GX)
 		case 2:
@@ -1512,7 +1630,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
 
 		if (0 == virgin) {
 			/* set the MAL IER ??? names may change with new spec ??? */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 			mal_ier =
 				MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
 				MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile
index 93416b57bf7..16dc8d62c05 100644
--- a/cpu/ppc4xx/Makefile
+++ b/cpu/ppc4xx/Makefile
@@ -30,7 +30,7 @@ SOBJS	= dcr.o
 COBJS	= 405gp_pci.o 4xx_enet.o \
 	  bedbug_405.o commproc.o \
 	  cpu.o cpu_init.o i2c.o interrupts.o \
-	  miiphy.o sdram.o serial.o \
+	  miiphy.o ndfc.o sdram.o serial.o \
 	  spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \
 	  440spe_pcie.o
 
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index bc51fbfdbed..94478dbb109 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -41,14 +41,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-
 #if defined(CONFIG_440)
 #define FREQ_EBC		(sys_info.freqEPB)
 #else
 #define FREQ_EBC		(sys_info.freqPLB / sys_info.pllExtBusDiv)
 #endif
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_405GP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 #define PCI_ASYNC
 
@@ -58,7 +59,8 @@ int pci_async_enabled(void)
 	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
 #endif
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -82,9 +84,10 @@ int pci_arbiter_enabled(void)
 	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-     defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -93,8 +96,10 @@ int pci_arbiter_enabled(void)
 }
 #endif
 
-#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
-     defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 
 #define I2C_BOOTROM
 
@@ -102,17 +107,75 @@ int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
 	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
-#endif
-
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
+#else
 	unsigned long val;
 
 	mfsdr(sdr_sdcs, val);
 	return (val & SDR0_SDCS_SDD);
 #endif
 }
+
+#if defined(CONFIG_440GX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (16 bits)",
+	"EBC (8 bits)",
+	"EBC (32 bits)",
+	"EBC (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"Reserved",
+	"I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define SDR0_PINSTP_SHIFT	30
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"I2C (Addr 0x50)",
+};
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"PCI",
+	"NAND (8 bits)",
+	"EBC (16 bits)",
+	"EBC (16 bits)",
+	"I2C (Addr 0x54)",
+	"PCI",
+	"I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PINSTP_SHIFT	29
+static char *bootstrap_str[] = {
+	"EBC (8 bits)",
+	"EBC (16 bits)",
+	"EBC (16 bits)",
+	"NAND (8 bits)",
+	"PCI",
+	"I2C (Addr 0x54)",
+	"PCI",
+	"I2C (Addr 0x52)",
+};
+#endif
+
+#if defined(SDR0_PINSTP_SHIFT)
+static int bootstrap_option(void)
+{
+	unsigned long val;
+
+	mfsdr(sdr_pinstp, val);
+	return ((val & 0xe0000000) >> SDR0_PINSTP_SHIFT);
+}
+#endif /* SDR0_PINSTP_SHIFT */
 #endif
 
 
@@ -244,6 +307,22 @@ int checkcpu (void)
 #endif /* CONFIG_440GR */
 #endif /* CONFIG_440 */
 
+	case PVR_440EPX1_RA:
+		puts("EPx Rev. A - Security/Kasumi support");
+		break;
+
+	case PVR_440EPX2_RA:
+		puts("EPx Rev. A - No Security/Kasumi support");
+		break;
+
+	case PVR_440GRX1_RA:
+		puts("GRx Rev. A - Security/Kasumi support");
+		break;
+
+	case PVR_440GRX2_RA:
+		puts("GRx Rev. A - No Security/Kasumi support");
+		break;
+
 	case PVR_440SP_RA:
 		puts("SP Rev. A");
 		break;
@@ -272,6 +351,10 @@ int checkcpu (void)
 
 #if defined(I2C_BOOTROM)
 	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
+#if defined(SDR0_PINSTP_SHIFT)
+	printf ("       Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
+	printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
+#endif
 #endif
 
 #if defined(CONFIG_PCI)
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 886f4051562..c5a9f02566a 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -57,12 +57,13 @@ static struct irq_action irq_vecs1[32]; /* For UIC1 */
 
 void uic1_interrupt( void * parms); /* UIC1 handler */
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 static struct irq_action irq_vecs2[32]; /* For UIC2 */
 void uic2_interrupt( void * parms); /* UIC2 handler */
 #endif /* CONFIG_440GX CONFIG_440SPE */
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 static struct irq_action irq_vecs3[32]; /* For UIC3 */
 void uic3_interrupt( void * parms); /* UIC3 handler */
 #endif /* CONFIG_440SPE */
@@ -119,12 +120,13 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 		irq_vecs1[vec].handler = NULL;
 		irq_vecs1[vec].arg = NULL;
 		irq_vecs1[vec].count = 0;
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		irq_vecs2[vec].handler = NULL;
 		irq_vecs2[vec].arg = NULL;
 		irq_vecs2[vec].count = 0;
 #endif /* CONFIG_440GX */
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 		irq_vecs3[vec].handler = NULL;
 		irq_vecs3[vec].arg = NULL;
 		irq_vecs3[vec].count = 0;
@@ -230,6 +232,32 @@ void external_interrupt(struct pt_regs *regs)
 
 } /* external_interrupt CONFIG_440GX */
 
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+void external_interrupt(struct pt_regs *regs)
+{
+	ulong uic_msr;
+
+	/*
+	 * Read masked interrupt status register to determine interrupt source
+	 */
+	/* 440 SPe uses base uic register */
+	uic_msr = mfdcr(uic0msr);
+
+	if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
+		uic1_interrupt(0);
+
+	if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
+		uic2_interrupt(0);
+
+	if (uic_msr & ~(UICB0_ALL))
+		uic0_interrupt(0);
+
+	mtdcr(uic0sr, uic_msr);
+
+	return;
+
+} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
+
 #elif defined(CONFIG_440SPE)
 void external_interrupt(struct pt_regs *regs)
 {
@@ -303,7 +331,8 @@ void external_interrupt(struct pt_regs *regs)
 }
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Handler for UIC0 interrupt */
 void uic0_interrupt( void * parms)
 {
@@ -394,7 +423,8 @@ void uic1_interrupt( void * parms)
 }
 #endif /* defined(CONFIG_440) */
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Handler for UIC2 interrupt */
 void uic2_interrupt( void * parms)
 {
@@ -496,7 +526,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 	int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64)) {
 		i = vec - 32;
 		irqa = irq_vecs1;
@@ -523,7 +554,8 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 	irqa[i].arg = arg;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64))
 		mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
 	else if (vec > 63)
@@ -546,7 +578,8 @@ void irq_free_handler (int vec)
 	int i = vec;
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64)) {
 		irqa = irq_vecs1;
 		i = vec - 32;
@@ -567,7 +600,8 @@ void irq_free_handler (int vec)
 #endif
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	if ((vec > 31) && (vec < 64))
 		mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
 	else if (vec > 63)
@@ -635,7 +669,8 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	printf("\n");
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	printf ("\nUIC 2\n");
 	printf ("Nr  Routine   Arg       Count\n");
 
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index aa580ed48f9..6b98025308f 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -173,7 +173,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
 	}
 	sta_reg = reg;		/* reg address */
 	/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
 		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
 #else
@@ -183,7 +184,9 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr,
 	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
 #endif
 	sta_reg = sta_reg | (addr << 5);	/* Phy address */
@@ -244,7 +247,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
 	sta_reg = 0;
 	sta_reg = reg;		/* reg address */
 	/* set clock (50Mhz) and read flags */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
 		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
 #else
@@ -254,7 +258,9 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr,
 	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
 #endif
 
-#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE)
+#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
 #endif
 	sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
new file mode 100644
index 00000000000..e4ab326bbfc
--- /dev/null
+++ b/cpu/ppc4xx/ndfc.c
@@ -0,0 +1,173 @@
+/*
+ * Overview:
+ *   Platform independend driver for NDFC (NanD Flash Controller)
+ *   integrated into EP440 cores
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *	Thomas Gleixner
+ *	Copyright 2006 IBM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
+
+#include <nand.h>
+#include <linux/mtd/ndfc.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+
+static u8 hwctl = 0;
+
+static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+	switch (cmd) {
+	case NAND_CTL_SETCLE:
+		hwctl |= 0x1;
+		break;
+
+	case NAND_CTL_CLRCLE:
+		hwctl &= ~0x1;
+		break;
+
+	case NAND_CTL_SETALE:
+		hwctl |= 0x2;
+		break;
+
+	case NAND_CTL_CLRALE:
+		hwctl &= ~0x2;
+		break;
+	}
+}
+
+static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	if (hwctl & 0x1)
+		out8(base + NDFC_CMD, byte);
+	else if (hwctl & 0x2)
+		out8(base + NDFC_ALE, byte);
+	else
+		out8(base + NDFC_DATA, byte);
+}
+
+static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	return (in8(base + NDFC_DATA));
+}
+
+static int ndfc_dev_ready(struct mtd_info *mtdinfo)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+
+	while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
+		;
+
+	return 1;
+}
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * Don't use these speedup functions in NAND boot image, since the image
+ * has to fit into 4kByte.
+ */
+
+/*
+ * Speedups for buffer read/write/verify
+ *
+ * NDFC allows 32bit read/write of data. So we can speed up the buffer
+ * functions. No further checking, as nand_base will always read/write
+ * page aligned.
+ */
+static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(;len > 0; len -= 4)
+		*p++ = in32(base + NDFC_DATA);
+}
+
+static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(; len > 0; len -= 4)
+		out32(base + NDFC_DATA, *p++);
+}
+
+static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
+{
+        struct nand_chip *this = mtdinfo->priv;
+        ulong base = (ulong) this->IO_ADDR_W;
+	uint32_t *p = (uint32_t *) buf;
+
+	for(; len > 0; len -= 4)
+		if (*p++ != in32(base + NDFC_DATA))
+			return -1;
+
+	return 0;
+}
+#endif /* #ifndef CONFIG_NAND_SPL */
+
+void board_nand_init(struct nand_chip *nand)
+{
+	nand->eccmode = NAND_ECC_SOFT;
+
+	nand->hwcontrol  = ndfc_hwcontrol;
+	nand->read_byte  = ndfc_read_byte;
+	nand->write_byte = ndfc_write_byte;
+	nand->dev_ready  = ndfc_dev_ready;
+
+#ifndef CONFIG_NAND_SPL
+	nand->write_buf  = ndfc_write_buf;
+	nand->read_buf   = ndfc_read_buf;
+	nand->verify_buf = ndfc_verify_buf;
+#else
+	/*
+	 * Setup EBC (CS0 only right now)
+	 */
+	mtdcr(ebccfga, xbcfg);
+	mtdcr(ebccfgd, 0xb8400000);
+
+	mtebc(pb0cr, CFG_EBC_PB0CR);
+	mtebc(pb0ap, CFG_EBC_PB0AP);
+#endif
+
+	/* Set NandFlash Core Configuration Register */
+	/* Chip select 3, 1col x 2 rows */
+	out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24));
+	out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222);
+}
+
+#endif
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c
index ad3ca6e819e..fab0d950063 100644
--- a/cpu/ppc4xx/serial.c
+++ b/cpu/ppc4xx/serial.c
@@ -264,10 +264,12 @@ int serial_tstc ()
 #endif	/* CONFIG_IOP480 */
 
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
+    defined(CONFIG_440)
 
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
 #define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
 #else
@@ -279,15 +281,34 @@ int serial_tstc ()
 #define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define CR0_MASK        0xdfffffff
-#define CR0_EXTCLK_ENA  0x00800000
-#define CR0_UDIV_POS    0
-#else
+#if defined(CONFIG_440GP)
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
-#endif /* CONFIG_440GX */
+#define UDIV_SUBTRACT	1
+#define UART0_SDR	cntrl0
+#define MFREG(a, d)	d = mfdcr(a)
+#define MTREG(a, d)	mtdcr(a, d)
+#else /* #if defined(CONFIG_440GP) */
+/* all other 440 PPC's access clock divider via sdr register */
+#define CR0_MASK        0xdfffffff
+#define CR0_EXTCLK_ENA  0x00800000
+#define CR0_UDIV_POS    0
+#define UDIV_SUBTRACT	0
+#define UART0_SDR	sdr_uart0
+#define UART1_SDR	sdr_uart1
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPe)
+#define UART2_SDR	sdr_uart2
+#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
+    defined(CONFIG_440GR) || defined(CONFIG_440GRx)
+#define UART3_SDR	sdr_uart3
+#endif
+#define MFREG(a, d)	mfsdr(a, d)
+#define MTREG(a, d)	mtsdr(a, d)
+#endif /* #if defined(CONFIG_440GP) */
 #elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
@@ -309,21 +330,15 @@ int serial_tstc ()
 #if defined(CONFIG_UART1_CONSOLE)
 #define ACTING_UART0_BASE	UART1_BASE
 #define ACTING_UART1_BASE	UART0_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#define UART0_SDR           sdr_uart1
-#define UART1_SDR           sdr_uart0
-#endif /* CONFIG_440GX */
 #else
 #define ACTING_UART0_BASE	UART0_BASE
 #define ACTING_UART1_BASE	UART1_BASE
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#define UART0_SDR           sdr_uart0
-#define UART1_SDR           sdr_uart1
-#endif /* CONFIG_440GX */
+#endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+#define UART_BASE	dev_base
+#else
+#define UART_BASE	ACTING_UART0_BASE
 #endif
 
 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
@@ -419,7 +434,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
 	*pbdiv = div/udiv;
 
 }
-#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
+#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */
 
 /*
  * Minimal serial functions needed to use one of the SMC ports
@@ -441,23 +456,9 @@ int serial_init(void)
 	unsigned long tmp;
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mfsdr(UART0_SDR,reg);
-		reg &= ~CR0_MASK;
-	} else {
-		mfsdr(UART1_SDR,reg);
-		reg &= ~CR0_MASK;
-	}
-#else
-	mfsdr(UART0_SDR,reg);
+	MFREG(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
-#endif
-#else
-	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#endif /* CONFIG_440GX */
+
 #ifdef CFG_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
@@ -471,47 +472,34 @@ int serial_init(void)
 	serial_divs (gd->baudrate, &udiv, &bdiv);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	defined(CONFIG_440SPE)
-	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mtsdr (UART0_SDR,reg);
-	} else {
-		mtsdr (UART1_SDR,reg);
-	}
-#else
-	mtsdr (UART0_SDR,reg);
+	reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS;	/* set the UART divisor */
+
+	/*
+	 * Configure input clock to baudrate generator for all
+	 * available serial ports here
+	 */
+	MTREG(UART0_SDR, reg);
+#if defined(UART1_SDR)
+	MTREG(UART1_SDR, reg);
 #endif
-#else
-	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
-	mtdcr (cntrl0, reg);
+#if defined(UART2_SDR)
+	MTREG(UART2_SDR, reg);
 #endif
-
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (dev_base + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (dev_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (dev_base + UART_LSR);	/* clear line status */
-	val = in8 (dev_base + UART_RBR);	/* read receive buffer */
-	out8 (dev_base + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
-#else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+#if defined(UART3_SDR)
+	MTREG(UART3_SDR, reg);
 #endif
+
+	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8(UART_BASE + UART_LSR);	/* clear line status */
+	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
+	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+
 	return (0);
 }
 
@@ -564,29 +552,17 @@ int serial_init (void)
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
 
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (dev_base + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (dev_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (dev_base + UART_LSR);	/* clear line status */
-	val = in8 (dev_base + UART_RBR);	/* read receive buffer */
-	out8 (dev_base + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
-#else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-#endif
+	out8(UART_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8(UART_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8(UART_BASE + UART_DLM, bdiv >> 8);	/* set baudrate divisor */
+	out8(UART_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8(UART_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8(UART_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8(UART_BASE + UART_LSR);	/* clear line status */
+	val = in8(UART_BASE + UART_RBR);	/* read receive buffer */
+	out8(UART_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8(UART_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+
 	return (0);
 }
 
@@ -598,55 +574,10 @@ void serial_setbrg_dev (unsigned long dev_base)
 void serial_setbrg (void)
 #endif
 {
-	unsigned long tmp;
-	unsigned long clk;
-	unsigned long udiv;
-	unsigned short bdiv;
-
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
-#else
-	clk = gd->cpu_clk;
-#endif
-
-#ifdef CONFIG_405EP
-	udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
-#else
-	udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
-#endif /* CONFIG_405EP */
-
-#if !defined(CFG_EXT_SERIAL_CLOCK) && \
-	( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
-	  defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
-	  defined(CONFIG_440SPE) )
-	serial_divs (gd->baudrate, &udiv, &bdiv);
-	tmp = udiv << CR0_UDIV_POS;		/* set the UART divisor */
-#if defined(CONFIG_SERIAL_MULTI)
-	if (UART0_BASE == dev_base) {
-		mtsdr (UART0_SDR, tmp);
-	} else {
-		mtsdr (UART1_SDR, tmp);
-	}
-#else
-	mtsdr (UART0_SDR, tmp);
-#endif
-
-#else
-
-	tmp = gd->baudrate * udiv * 16;
-	bdiv = (clk + tmp / 2) / tmp;
-#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */
-
 #if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	serial_init_dev(dev_base);
 #else
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	serial_init();
 #endif
 }
 
@@ -667,19 +598,11 @@ void serial_putc (const char c)
 
 	/* check THRE bit, wait for transmiter available */
 	for (i = 1; i < 3500; i++) {
-#if defined(CONFIG_SERIAL_MULTI)
-		if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
-#else
-		if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
-#endif
+		if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
 			break;
 		udelay (100);
 	}
-#if defined(CONFIG_SERIAL_MULTI)
-	out8 (dev_base + UART_THR, c);	/* put character out */
-#else
-	out8 (ACTING_UART0_BASE + UART_THR, c);	/* put character out */
-#endif
+	out8 (UART_BASE + UART_THR, c);	/* put character out */
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -709,11 +632,7 @@ int serial_getc (void)
 #if defined(CONFIG_HW_WATCHDOG)
 		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 #endif	/* CONFIG_HW_WATCHDOG */
-#if defined(CONFIG_SERIAL_MULTI)
-		status = in8 (dev_base + UART_LSR);
-#else
-		status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+		status = in8 (UART_BASE + UART_LSR);
 		if ((status & asyncLSRDataReady1) != 0x0) {
 			break;
 		}
@@ -721,22 +640,14 @@ int serial_getc (void)
 				asyncLSROverrunError1 |
 				asyncLSRParityError1  |
 				asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
-			out8 (dev_base + UART_LSR,
-#else
-			out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+			out8 (UART_BASE + UART_LSR,
 			      asyncLSRFramingError1 |
 			      asyncLSROverrunError1 |
 			      asyncLSRParityError1  |
 			      asyncLSRBreakInterrupt1);
 		}
 	}
-#if defined(CONFIG_SERIAL_MULTI)
-	return (0x000000ff & (int) in8 (dev_base));
-#else
-	return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
-#endif
+	return (0x000000ff & (int) in8 (UART_BASE));
 }
 
 #if defined(CONFIG_SERIAL_MULTI)
@@ -747,11 +658,7 @@ int serial_tstc (void)
 {
 	unsigned char status;
 
-#if defined(CONFIG_SERIAL_MULTI)
-	status = in8 (dev_base + UART_LSR);
-#else
-	status = in8 (ACTING_UART0_BASE + UART_LSR);
-#endif
+	status = in8 (UART_BASE + UART_LSR);
 	if ((status & asyncLSRDataReady1) != 0x0) {
 		return (1);
 	}
@@ -759,11 +666,7 @@ int serial_tstc (void)
 			asyncLSROverrunError1 |
 			asyncLSRParityError1  |
 			asyncLSRBreakInterrupt1 )) != 0) {
-#if defined(CONFIG_SERIAL_MULTI)
-		out8 (dev_base + UART_LSR,
-#else
-		out8 (ACTING_UART0_BASE + UART_LSR,
-#endif
+		out8 (UART_BASE + UART_LSR,
 		      asyncLSRFramingError1 |
 		      asyncLSROverrunError1 |
 		      asyncLSRParityError1  |
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index e552c034733..2d16a83420a 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -199,7 +199,8 @@ ulong get_PCI_freq (void)
 
 #elif defined(CONFIG_440)
 
-#if  defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 void get_sys_info (sys_info_t *sysInfo)
 {
 	unsigned long temp;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 60ed2d54536..5a1ab386b18 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -117,12 +117,16 @@
 
 	.extern ext_bus_cntlr_init
 	.extern sdram_init
+#ifdef CONFIG_NAND_U_BOOT
+	.extern reconfig_tlb0
+#endif
 
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
+#if !defined(CONFIG_NAND_SPL)
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
@@ -136,6 +140,18 @@
 	GOT_ENTRY(_end)
 	GOT_ENTRY(__bss_start)
 	END_GOT
+#endif /* CONFIG_NAND_SPL */
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+	/*
+	 * NAND U-Boot image is started from offset 0
+	 */
+	.text
+	bl	reconfig_tlb0
+	GET_GOT
+	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
+	bl	board_init_f
+#endif
 
 /*
  * 440 Startup -- on reset only the top 4k of the effective
@@ -150,11 +166,21 @@
  */
 
 #if defined(CONFIG_440)
+#if !defined(CONFIG_NAND_SPL)
     .section .bootpg,"ax"
+#endif
     .globl _start_440
 
 /**************************************************************************/
 _start_440:
+        /*--------------------------------------------------------------------+
+        | 440EPX BUP Change - Hardware team request
+        +--------------------------------------------------------------------*/
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+	sync
+	nop
+	nop
+#endif
 	/*----------------------------------------------------------------+
 	| Core bug fix.  Clear the esr
 	+-----------------------------------------------------------------*/
@@ -171,15 +197,19 @@ _start_440:
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)  /* NOTE: 440GX adds machine check status regs */
+	/* NOTE: 440GX adds machine check status regs */
+#if defined(CONFIG_440) && !defined(CONFIG_440GP)
 	mtspr	mcsrr0,r0
 	mtspr	mcsrr1,r0
-	mfspr	r1, mcsr
+	mfspr	r1,mcsr
 	mtspr	mcsr,r1
 #endif
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
+	mfspr	r1,dbcr0
+	andis.	r1, r1, 0x8000	/* test DBCR0[EDM] bit			*/
+	bne	skip_debug_init	/* if set, don't clear debug register	*/
 	mtspr	dbcr0,r0
 	mtspr	dbcr1,r0
 	mtspr	dbcr2,r0
@@ -193,6 +223,7 @@ _start_440:
 
 	mfspr	r1,dbsr
 	mtspr	dbsr,r1		/* Clear all valid bits */
+skip_debug_init:
 
 	/*----------------------------------------------------------------*/
 	/* CCR0 init */
@@ -352,7 +383,53 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	/*----------------------------------------------------------------*/
 	/* Continue from 'normal' start */
 	/*----------------------------------------------------------------*/
-2:	bl	3f
+2:
+
+#if defined(CONFIG_NAND_SPL)
+	/*
+	 * Enable internal SRAM
+	 */
+	lis	r2,0x7fff
+	ori	r2,r2,0xffff
+	mfdcr	r1,isram0_dpc
+	and	r1,r1,r2		/* Disable parity check */
+	mtdcr	isram0_dpc,r1
+	mfdcr	r1,isram0_pmeg
+	and	r1,r1,r2		/* Disable pwr mgmt */
+	mtdcr	isram0_pmeg,r1
+
+	/*
+	 * Copy SPL from cache into internal SRAM
+	 */
+	li	r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
+	mtctr	r4
+	lis	r2,CFG_NAND_BOOT_SPL_SRC@h
+	ori	r2,r2,CFG_NAND_BOOT_SPL_SRC@l
+	lis	r3,CFG_NAND_BOOT_SPL_DST@h
+	ori	r3,r3,CFG_NAND_BOOT_SPL_DST@l
+spl_loop:
+	lwzu	r4,4(r2)
+	stwu	r4,4(r3)
+	bdnz	spl_loop
+
+	/*
+	 * Jump to code in RAM
+	 */
+	bl	00f
+00:	mflr	r10
+	lis	r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
+	ori	r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
+	sub	r10,r10,r3
+	addi	r10,r10,28
+	mtlr	r10
+	blr
+
+start_ram:
+	sync
+	isync
+#endif
+
+	bl	3f
 	b	_start
 
 3:	li	r0,0
@@ -366,6 +443,7 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
+#ifndef CONFIG_NAND_SPL
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
@@ -379,6 +457,7 @@ version_string:
  * location (0x100) is where the CriticalInput Execption should be.
  */
 	. = EXC_OFF_SYS_RESET
+#endif
 	.globl	_start
 _start:
 
@@ -417,7 +496,8 @@ _start:
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+#ifdef CFG_INIT_RAM_DCACHE
 	/* Clear Dcache to use as RAM */
 	addis	r3,r0,CFG_INIT_RAM_ADDR@h
 	ori	r3,r3,CFG_INIT_RAM_ADDR@l
@@ -433,19 +513,22 @@ _start:
 	dcbz	r0,r3
 	addi	r3,r3,32
 	bdnz	..d_ag
-#else
-#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#endif /* CFG_INIT_RAM_DCACHE */
+
+	/* 440EP & 440GR are only 440er PPC's without internal SRAM */
+#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
+	/* not all PPC's have internal SRAM usable as L2-cache */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	mtdcr	l2_cache_cfg,r0		/* Ensure L2 Cache is off */
 #endif
-	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 
-	li	r2,0x7fff
+	lis	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,isram0_dpc
 	and	r1,r1,r2		/* Disable parity check */
 	mtdcr	isram0_dpc,r1
 	mfdcr	r1,isram0_pmeg
-	andis.	r1,r1,r2		/* Disable pwr mgmt */
+	and	r1,r1,r2		/* Disable pwr mgmt */
 	mtdcr	isram0_pmeg,r1
 
 	lis	r1,0x8000		/* BAS = 8000_0000 */
@@ -474,11 +557,12 @@ _start:
 	lis	r1, 0x0003
 	ori	r1,r1, 0x0984		/* fourth 64k */
 	mtdcr	isram0_sb3cr,r1
-#else
+#elif defined(CONFIG_440GP)
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
+	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 #endif
-#endif
+#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
@@ -495,10 +579,14 @@ _start:
 	stwu	r1,-8(r1)		/* Save back chain and move SP */
 	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
 
+#ifdef CONFIG_NAND_SPL
+	bl	nand_boot		/* will not return */
+#else
 	GET_GOT
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
 	bl	board_init_f
+#endif
 
 #endif /* CONFIG_440 */
 
@@ -808,6 +896,7 @@ _start:
 	/*----------------------------------------------------------------------- */
 
 
+#ifndef CONFIG_NAND_SPL
 /*****************************************************************************/
 	.globl	_start_of_vectors
 _start_of_vectors:
@@ -1013,6 +1102,7 @@ crit_return:
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfci
+#endif /* CONFIG_NAND_SPL */
 
 /* Cache functions.
 */
@@ -1254,6 +1344,7 @@ ppcSync:
 
 /*------------------------------------------------------------------------------*/
 
+#ifndef CONFIG_NAND_SPL
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
@@ -1267,7 +1358,9 @@ ppcSync:
  */
 	.globl	relocate_code
 relocate_code:
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SPE)
 	/*
 	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
 	 * to speed up the boot process. Now this cache needs to be disabled.
@@ -1482,22 +1575,22 @@ trap_init:
 	cmplw	0, r7, r8
 	blt	4b
 
-#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE)
+#if !defined(CONFIG_440)
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r7,r7,0x0002		/* set CE bit (Critical Exceptions) */
 	mtmsr	r7			/* change MSR */
 #else
-	bl	__440gx_msr_set
-	b	__440gx_msr_continue
+	bl	__440_msr_set
+	b	__440_msr_continue
 
-__440gx_msr_set:
+__440_msr_set:
 	addi	r7,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r7,r7,0x0002		/* set CE bit (Critical Exceptions) */
 	mtspr	srr1,r7
 	mflr	r7
 	mtspr	srr0,r7
 	rfi
-__440gx_msr_continue:
+__440_msr_continue:
 #endif
 
 	mtlr	r4			/* restore link register	*/
@@ -1516,6 +1609,7 @@ trap_reloc:
 	stw	r0, 4(r7)
 
 	blr
+#endif /* CONFIG_NAND_SPL */
 
 
 /**************************************************************************/
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index bb5765891f8..ab852c525cf 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -76,7 +76,7 @@
 #define m16_swap(x) swap_16(x)
 #define m32_swap(x) swap_32(x)
 
-#ifdef CONFIG_440EP
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 #define ohci_cpu_to_le16(x) (x)
 #define ohci_cpu_to_le32(x) (x)
 #else
@@ -1599,7 +1599,11 @@ int usb_lowlevel_init(void)
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#if defined(CONFIG_440EP)
+ 	gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+#elif defined(CONFIG_440EPX)
+	gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
+#endif
 
 	gohci.flags = 0;
 	gohci.slot_name = "ppc440";
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c
index 8262c54bef1..6140d2a9089 100644
--- a/cpu/ppc4xx/usbdev.c
+++ b/cpu/ppc4xx/usbdev.c
@@ -3,7 +3,7 @@
 #include <common.h>
 #include <asm/processor.h>
 
-#ifdef CONFIG_440EP
+#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && (CONFIG_COMMANDS & CFG_CMD_USB)
 
 #include <usb.h>
 #include "usbdev.h"
@@ -186,6 +186,21 @@ int usbInt(void)
 	return 0;
 }
 
+#if defined(CONFIG_440EPX)
+void usb_dev_init()
+{
+	printf("USB 2.0 Device init\n");
+
+	/*usb dev init */
+	*(unsigned char *)USB2D0_POWER_8 = 0xa1;	/* 2.0 */
+
+	/*enable interrupts */
+	*(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
+
+	irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt,
+			    NULL);
+}
+#else
 void usb_dev_init()
 {
 #ifdef USB_2_0_DEVICE
@@ -210,5 +225,6 @@ void usb_dev_init()
 	irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
 			    NULL);
 }
+#endif
 
-#endif				/*CONFIG_440EP */
+#endif /* CONFIG_440EP || CONFIG_440EPX */
diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h
index 93cef026a3f..70e436aab23 100644
--- a/cpu/ppc4xx/vecnum.h
+++ b/cpu/ppc4xx/vecnum.h
@@ -31,7 +31,94 @@
 #ifndef _VECNUMS_H_
 #define _VECNUMS_H_
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440EPX) || defined(CONFIG_440_GRX)
+
+/* UIC 0 */
+#define VECNUM_U0                   0  /* UART 0                        */
+#define VECNUM_U1                   1  /* UART 1                        */
+#define VECNUM_IIC0                 2  /* IIC                           */
+#define VECNUM_KRD                  3  /* Kasumi Ready for data         */
+#define VECNUM_KDA                  4  /* Kasumi Data Available         */
+#define VECNUM_PCRW                 5  /* PCI command register write    */
+#define VECNUM_PPM                  6  /* PCI power management          */
+#define VECNUM_IIC1                 7  /* IIC                           */
+#define VECNUM_SPI                  8  /* SPI                           */
+#define VECNUM_EPCISER              9  /* External PCI SERR             */
+#define VECNUM_MTE                 10  /* MAL TXEOB                     */
+#define VECNUM_MRE                 11  /* MAL RXEOB                     */
+#define VECNUM_D0                  12  /* DMA channel 0                 */
+#define VECNUM_D1                  13  /* DMA channel 1                 */
+#define VECNUM_D2                  14  /* DMA channel 2                 */
+#define VECNUM_D3                  15  /* DMA channel 3                 */
+#define VECNUM_UD0                 16  /* UDMA irq 0                    */
+#define VECNUM_UD1                 17  /* UDMA irq 1                    */
+#define VECNUM_UD2                 18  /* UDMA irq 2                    */
+#define VECNUM_UD3                 19  /* UDMA irq 3                    */
+#define VECNUM_HSB2D               20  /* USB2.0 Device                 */
+#define VECNUM_USBDEV		   20  /* USB 1.1/USB 2.0 Device        */
+#define VECNUM_OHCI1               21  /* USB2.0 Host OHCI irq 1        */
+#define VECNUM_OHCI2               22  /* USB2.0 Host OHCI irq 2        */
+#define VECNUM_EIP94               23  /* Security EIP94                */
+#define VECNUM_ETH0                24  /* Emac 0                        */
+#define VECNUM_ETH1                25  /* Emac 1                        */
+#define VECNUM_EHCI                26  /* USB2.0 Host EHCI              */
+#define VECNUM_EIR4                27  /* External interrupt 4          */
+#define VECNUM_UIC2NC              28  /* UIC2 non-critical interrupt   */
+#define VECNUM_UIC2C               29  /* UIC2 critical interrupt       */
+#define VECNUM_UIC1NC              30  /* UIC1 non-critical interrupt   */
+#define VECNUM_UIC1C               31  /* UIC1 critical interrupt       */
+
+/* UIC 1 */
+#define VECNUM_MS           (32 +  0)  /* MAL SERR                      */
+#define VECNUM_MTDE         (32 +  1)  /* MAL TXDE                      */
+#define VECNUM_MRDE         (32 +  2)  /* MAL RXDE                      */
+#define VECNUM_U2           (32 +  3)  /* UART 2                        */
+#define VECNUM_U3           (32 +  4)  /* UART 3                        */
+#define VECNUM_EBCO         (32 +  5)  /* EBCO interrupt status         */
+#define VECNUM_NDFC         (32 +  6)  /* NDFC                          */
+#define VECNUM_KSLE         (32 +  7)  /* KASUMI slave error            */
+#define VECNUM_CT5          (32 +  8)  /* GPT compare timer 5           */
+#define VECNUM_CT6          (32 +  9)  /* GPT compare timer 6           */
+#define VECNUM_PLB34I0      (32 + 10)  /* PLB3X4X MIRQ0                 */
+#define VECNUM_PLB34I1      (32 + 11)  /* PLB3X4X MIRQ1                 */
+#define VECNUM_PLB34I2      (32 + 12)  /* PLB3X4X MIRQ2                 */
+#define VECNUM_PLB34I3      (32 + 13)  /* PLB3X4X MIRQ3                 */
+#define VECNUM_PLB34I4      (32 + 14)  /* PLB3X4X MIRQ4                 */
+#define VECNUM_PLB34I5      (32 + 15)  /* PLB3X4X MIRQ5                 */
+#define VECNUM_CT0          (32 + 16)  /* GPT compare timer 0           */
+#define VECNUM_CT1          (32 + 17)  /* GPT compare timer 1           */
+#define VECNUM_EIR7         (32 + 18)  /* External interrupt 7          */
+#define VECNUM_EIR8         (32 + 19)  /* External interrupt 8          */
+#define VECNUM_EIR9         (32 + 20)  /* External interrupt 9          */
+#define VECNUM_CT2          (32 + 21)  /* GPT compare timer 2           */
+#define VECNUM_CT3          (32 + 22)  /* GPT compare timer 3           */
+#define VECNUM_CT4          (32 + 23)  /* GPT compare timer 4           */
+#define VECNUM_SRE          (32 + 24)  /* Serial ROM error              */
+#define VECNUM_GPTDC        (32 + 25)  /* GPT decrementer pulse         */
+#define VECNUM_RSVD0        (32 + 26)  /* Reserved                      */
+#define VECNUM_EPCIPER      (32 + 27)  /* External PCI PERR             */
+#define VECNUM_EIR0         (32 + 28)  /* External interrupt 0          */
+#define VECNUM_EWU0         (32 + 29)  /* Ethernet 0 wakeup             */
+#define VECNUM_EIR1         (32 + 30)  /* External interrupt 1          */
+#define VECNUM_EWU1         (32 + 31)  /* Ethernet 1 wakeup             */
+
+#define VECNUM_TXDE         VECNUM_MTDE
+#define VECNUM_RXDE         VECNUM_MRDE
+
+/* UIC 2 */
+#define VECNUM_EIR5         (62 +  0)  /* External interrupt 5          */
+#define VECNUM_EIR6         (62 +  1)  /* External interrupt 6          */
+#define VECNUM_OPB          (62 +  2)  /* OPB to PLB bridge int stat    */
+#define VECNUM_EIR2         (62 +  3)  /* External interrupt 2          */
+#define VECNUM_EIR3         (62 +  4)  /* External interrupt 3          */
+#define VECNUM_DDR2         (62 +  5)  /* DDR2 sdram                    */
+#define VECNUM_MCTX0        (62 +  6)  /* MAl intp coalescence TX0      */
+#define VECNUM_MCTX1        (62 +  7)  /* MAl intp coalescence TX1      */
+#define VECNUM_MCTR0        (62 +  8)  /* MAl intp coalescence TR0      */
+#define VECNUM_MCTR1        (62 +  9)  /* MAl intp coalescence TR1      */
+
+#elif defined(CONFIG_440SPE)
+
 /* UIC 0 */
 #define VECNUM_U0           0           /* UART0                        */
 #define VECNUM_U1           1           /* UART1                        */
diff --git a/doc/README.nand-boot-ppc440 b/doc/README.nand-boot-ppc440
new file mode 100644
index 00000000000..a82a10ee6a5
--- /dev/null
+++ b/doc/README.nand-boot-ppc440
@@ -0,0 +1,36 @@
+-----------------------------
+NAND boot on PPC440 platforms
+-----------------------------
+
+This document describes the U-Boot NAND boot feature as it
+is implemented for the AMCC Sequoia (PPC440EPx) board.
+
+The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
+completely without NOR FLASH. This can be done by using the NAND
+boot feature of the 440 NAND flash controller (NDFC).
+
+Here a short desciption of the different boot stages:
+
+a) IPL (Initial Program Loader, integrated inside CPU)
+------------------------------------------------------
+Will load first 4k from NAND (SPL) into cache and execute it from there.
+
+b) SPL (Secondary Program Loader)
+---------------------------------
+Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+controller and the NAND controller so that the special U-Boot image can be
+loaded from NAND to SDRAM.
+This special image is build in the directory "nand_spl".
+
+c) NUB (NAND U-Boot)
+--------------------
+This NAND U-Boot (NUB) is a special U-Boot version which can be started
+from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+
+On 440EPx the SPL is copied to internal SRAM before the NAND controller
+is set up. While still running from cache, I experienced problems accessing
+the NAND controller.
+
+
+September 07 2006, Stefan Roese <sr@denx.de>
diff --git a/dtt/lm75.c b/dtt/lm75.c
index 59daa453976..63f3b7551e9 100644
--- a/dtt/lm75.c
+++ b/dtt/lm75.c
@@ -146,8 +146,13 @@ static int _dtt_init(int sensor)
     /*
      * Setup configuraton register
      */
+#ifdef CONFIG_DTT_AD7414
+    /* config = alert active low and disabled */
+    val = 0x60;
+#else
     /* config = 6 sample integration, int mode, active low, and enable */
     val = 0x18;
+#endif
     if (dtt_write(sensor, DTT_CONFIG, val) != 0)
 	return 1;
 
diff --git a/include/405_mal.h b/include/405_mal.h
index 05985869534..2a421848b4b 100644
--- a/include/405_mal.h
+++ b/include/405_mal.h
@@ -92,7 +92,7 @@
 #define MAL_ESR_PBEI	  0x00000001
       /* ^^			 ^^   */
       /* Mal IER		      */
-#ifdef CONFIG_440SPE
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define MAL_IER_PT	  0x00000080
 #define MAL_IER_PRE	  0x00000040
 #define MAL_IER_PWE	  0x00000020
diff --git a/include/440_i2c.h b/include/440_i2c.h
index 9c90a9e3c48..0c2bf362730 100644
--- a/include/440_i2c.h
+++ b/include/440_i2c.h
@@ -1,7 +1,8 @@
 #ifndef _440_i2c_h_
 #define _440_i2c_h_
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
 #else
 #define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 44b23f1eb4c..bbd3497c50e 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -728,6 +728,10 @@
 #define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
 #define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D8 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218DC /* 440GRX rev A without Security / Kasumi */
 #define PVR_440GX_RA	0x51B21850
 #define PVR_440GX_RB	0x51B21851
 #define PVR_440GX_RC	0x51B21892
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index f7aa55f3343..794a6d49747 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -108,7 +108,8 @@ typedef struct bd_info {
 #endif
 
 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
 	int		bi_iic_fast[2];		/* Use fast i2c mode */
 #endif
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index cd4339b5822..4961011b5cd 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -73,6 +73,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(4 << 10)
 #define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h
index 50c1c4fd4cb..23bdfc8dfb9 100644
--- a/include/configs/pcs440ep.h
+++ b/include/configs/pcs440ep.h
@@ -63,6 +63,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
new file mode 100644
index 00000000000..d3fcc032aa5
--- /dev/null
+++ b/include/configs/sequoia.h
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#define CFG_BOOT_BASE_ADDR	0xf0000000
+#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
+#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
+#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000
+
+/* Don't change either of these */
+#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/
+
+#define CFG_USB2D0_BASE		0xe0000100
+#define CFG_USB_DEVICE		0xe0000000
+#define CFG_USB_HOST		0xe0000400
+#define CFG_BCSR_BASE		0xc0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#if 0
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache		*/
+#else
+#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
+#endif
+
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
+#endif
+#if 0
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CFG_NAND_BASE		CFG_NAND_ADDR
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 4k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ * On 440EPx the SPL is copied to SDRAM before the NAND controller is
+ * set up. While still running from cache, I experienced problems accessing
+ * the NAND controller.	sr - 2006-08-25
+ */
+#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
+#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
+#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
+#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
+#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
+#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
+
+/*
+ * Now the NAND chip has to be defined (no autodetection used!)
+ */
+#define CFG_NAND_PAGE_SIZE	(512)		/* NAND chip page size		*/
+#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
+#define CFG_NAND_PAGE_COUNT	(32)		/* NAND chip page count		*/
+#define CFG_NAND_BAD_BLOCK_POS	(5)		/* Location of bad block marker	*/
+#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
+
+#ifdef CFG_ENV_IS_IN_NAND
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE)
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CFG_MBYTES_SDRAM        (256)    /* 256MB			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200		/* Size of Environment vars	*/
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#define CONFIG_PREBOOT	"echo;"						\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sequoia\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/sequoia/uImage\0"				\
+	"kernel_addr=FE000000\0"					\
+	"ramdisk_addr=FE180000\0"					\
+	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_M88E1111_PHY	1
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
+			       CFG_CMD_ASKENV	|	\
+			       CFG_CMD_DHCP	|	\
+			       CFG_CMD_DTT	|	\
+			       CFG_CMD_DIAG	|	\
+			       CFG_CMD_EEPROM	|	\
+			       CFG_CMD_ELF	|	\
+			       CFG_CMD_FAT	|	\
+			       CFG_CMD_I2C	|	\
+			       CFG_CMD_IRQ	|	\
+			       CFG_CMD_MII	|	\
+			       CFG_CMD_NAND	|	\
+			       CFG_CMD_NET	|	\
+			       CFG_CMD_NFS	|	\
+			       CFG_CMD_PCI	|	\
+			       CFG_CMD_PING	|	\
+			       CFG_CMD_REGINFO	|	\
+			       CFG_CMD_SDRAM	|	\
+			       CFG_CMD_USB    )
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH		CFG_FLASH_BASE
+#define CFG_NAND		0xD0000000
+#define CFG_CPLD		0xC0000000
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x03017300
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0xba000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x018003c0
+#define CFG_EBC_PB3CR		(CFG_NAND | 0x1c000)
+#else
+#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
+/* Memory Bank 3 (NOR-FLASH) initialization					*/
+#define CFG_EBC_PB3AP		0x03017300
+#define CFG_EBC_PB3CR		(CFG_FLASH | 0xba000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization					*/
+#define CFG_EBC_PB0AP		0x018003c0
+#define CFG_EBC_PB0CR		(CFG_NAND | 0x1c000)
+#endif
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CFG_EBC_PB2AP		0x24814580
+#define CFG_EBC_PB2CR		(CFG_CPLD | 0x38000)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ *----------------------------------------------------------------------*/
+#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	      /* ...			            */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
index cf42b666b00..bcafd8ba8b3 100644
--- a/include/configs/yellowstone.h
+++ b/include/configs/yellowstone.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 86a85b8a6d3..3d7b4a2f4bc 100644
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -65,6 +65,7 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
 #define CFG_INIT_RAM_END	(8 << 10)
 #define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
index 460cd45c808..fe55087ea93 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/mtd/compat.h
@@ -31,11 +31,13 @@
 #define max_t(type,x,y) \
 	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
 
+#ifndef BUG
 #define BUG() do { \
 	printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
 } while (0)
 
 #define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
 
 #define likely(x)	__builtin_expect(!!(x), 1)
 #define unlikely(x)	__builtin_expect(!!(x), 0)
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
new file mode 100644
index 00000000000..d0558a98262
--- /dev/null
+++ b/include/linux/mtd/ndfc.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/linux/mtd/ndfc.h
+ *
+ *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD		0x00
+#define NDFC_ALE		0x04
+#define NDFC_DATA		0x08
+#define NDFC_ECC		0x10
+#define NDFC_BCFG0		0x30
+#define NDFC_BCFG1		0x34
+#define NDFC_BCFG2		0x38
+#define NDFC_BCFG3		0x3c
+#define NDFC_CCR		0x40
+#define NDFC_STAT		0x44
+#define NDFC_HWCTL		0x48
+#define NDFC_REVID		0x50
+
+#define NDFC_STAT_IS_READY	0x01000000
+
+#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS		4
+
+struct ndfc_controller_settings {
+	uint32_t	ccr_settings;
+	uint64_t	ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+	uint32_t	bank_settings;
+};
+
+#endif
diff --git a/include/ppc440.h b/include/ppc440.h
index d5a9f66a419..c4a3ed54835 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -82,7 +82,10 @@
 #define	 ivor13 0x19d	/* interrupt vector offset register 13 */
 #define	 ivor14 0x19e	/* interrupt vector offset register 14 */
 #define	 ivor15 0x19f	/* interrupt vector offset register 15 */
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 #define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
 #define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
 #define	 mcsr	0x23c	/* machine check status register */
@@ -151,7 +154,18 @@
 #define sdr_ecid1	0x0081
 #define sdr_ecid2	0x0082
 #define sdr_jtag	0x00c0
+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
 #define sdr_ddrdl	0x00e0
+#else
+#define sdr_cfg		0x00e0
+#define SDR_CFG_LT2_MASK          0x01000000 /* Leakage test 2*/
+#define SDR_CFG_64_32BITS_MASK    0x01000000 /* Switch DDR 64 bits or 32 bits */
+#define SDR_CFG_32BITS            0x00000000  /* 32 bits */
+#define SDR_CFG_64BITS            0x01000000  /* 64 bits */
+#define SDR_CFG_MC_V2518_MASK     0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
+#define SDR_CFG_MC_V25            0x00000000  /* 2.5 V */
+#define SDR_CFG_MC_V18            0x02000000  /* 1.8 V */
+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
 #define sdr_ebc		0x0100
 #define sdr_uart0	0x0120	/* UART0 Config */
 #define sdr_uart1	0x0121	/* UART1 Config */
@@ -180,6 +194,54 @@
 #define sdr_plbtr	0x4200
 #define sdr_mfr		0x4300	/* SDR0_MFR reg */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
+#define DDR0_00	0x00
+#define DDR0_01	0x01
+#define DDR0_02	0x02
+#define DDR0_03	0x03
+#define DDR0_04	0x04
+#define DDR0_05	0x05
+#define DDR0_06	0x06
+#define DDR0_07	0x07
+#define DDR0_08	0x08
+#define DDR0_09	0x09
+#define DDR0_10	0x0A
+#define DDR0_11	0x0B
+#define DDR0_12	0x0C
+#define DDR0_13	0x0D
+#define DDR0_14	0x0E
+#define DDR0_15	0x0F
+#define DDR0_16	0x10
+#define DDR0_17	0x11
+#define DDR0_18	0x12
+#define DDR0_19	0x13
+#define DDR0_20	0x14
+#define DDR0_21	0x15
+#define DDR0_22	0x16
+#define DDR0_23	0x17
+#define DDR0_24	0x18
+#define DDR0_25	0x19
+#define DDR0_26	0x1A
+#define DDR0_27	0x1B
+#define DDR0_28	0x1C
+#define DDR0_29	0x1D
+#define DDR0_30	0x1E
+#define DDR0_31	0x1F
+#define DDR0_32	0x20
+#define DDR0_33	0x21
+#define DDR0_34	0x22
+#define DDR0_35	0x23
+#define DDR0_36	0x24
+#define DDR0_37	0x25
+#define DDR0_38	0x26
+#define DDR0_39	0x27
+#define DDR0_40	0x28
+#define DDR0_41	0x29
+#define DDR0_42	0x2A
+#define DDR0_43	0x2B
+#define DDR0_44	0x2C
+#endif /*CONFIG_440EPX*/
+
 /*-----------------------------------------------------------------------------
  | SDRAM Controller
  +----------------------------------------------------------------------------*/
@@ -787,7 +849,8 @@
 #define xbcfg		0x23	/* external bus configuration reg	*/
 #define xbcid		0x24	/* external bus core id reg		*/
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PLB4 to PLB3 Bridge OUT */
 #define P4P3_DCR_BASE           0x020
@@ -877,6 +940,7 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -918,6 +982,178 @@
 #define   SDR0_USB0_LEEN_DISABLE      0x00000000      /* Little Endian Disable */
 #define   SDR0_USB0_LEEN_ENABLE       0x00000001      /* Little Endian Enable */
 
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
+#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR_USB2D0CR                 0x0320
+#define   SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK   0x00000004    /* USB 2.0 Device/EBC Master Selection */
+#define   SDR0_USB2D0CR_USB2DEV_SELECTION      0x00000004    /* USB 2.0 Device Selection */
+#define   SDR0_USB2D0CR_EBC_SELECTION          0x00000000    /* EBC Selection */
+
+#define   SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK   0x00000002    /* USB Device Interface Selection */
+#define   SDR0_USB2D0CR_USB20D_DEVSEL          0x00000000      /* USB2.0 Device Selected */
+#define   SDR0_USB2D0CR_USB11D_DEVSEL          0x00000002      /* USB1.1 Device Selected */
+
+#define   SDR0_USB2D0CR_LEEN_MASK              0x00000001    /* Little Endian selection */
+#define   SDR0_USB2D0CR_LEEN_DISABLE           0x00000000      /* Little Endian Disable */
+#define   SDR0_USB2D0CR_LEEN_ENABLE            0x00000001      /* Little Endian Enable */
+
+/* USB2 Host Control Register */
+#define SDR0_USB2H0CR                0x0340
+#define   SDR0_USB2H0CR_WDINT_MASK             0x00000001 /* Host UTMI Word Interface */
+#define   SDR0_USB2H0CR_WDINT_8BIT_60MHZ       0x00000000  /* 8-bit/60MHz */
+#define   SDR0_USB2H0CR_WDINT_16BIT_30MHZ      0x00000001  /* 16-bit/30MHz */
+#define   SDR0_USB2H0CR_EFLADJ_MASK            0x0000007e /* EHCI Frame Length Adjustment */
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1                    0x4101
+#define   SDR0_PFC1_U1ME_MASK                  0x02000000    /* UART1 Mode Enable */
+#define   SDR0_PFC1_U1ME_DSR_DTR               0x00000000      /* UART1 in DSR/DTR Mode */
+#define   SDR0_PFC1_U1ME_CTS_RTS               0x02000000      /* UART1 in CTS/RTS Mode */
+
+#define   SDR0_PFC1_SELECT_MASK                0x01C00000 /* Ethernet Pin Select EMAC 0 */
+#define   SDR0_PFC1_SELECT_CONFIG_1_1          0x00C00000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_2            0x00C00000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_3            0x01000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_4            0x01400000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_5            0x01800000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC1_SELECT_CONFIG_6            0x00800000   /* 2xSMII  using  ZMII bridge */
+
+#define   SDR0_PFC1_U0ME_MASK                  0x00080000    /* UART0 Mode Enable */
+#define   SDR0_PFC1_U0ME_DSR_DTR               0x00000000      /* UART0 in DSR/DTR Mode */
+#define   SDR0_PFC1_U0ME_CTS_RTS               0x00080000      /* UART0 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0IM_MASK                  0x00040000    /* UART0 Interface Mode */
+#define   SDR0_PFC1_U0IM_8PINS                 0x00000000      /* UART0 Interface Mode 8 pins */
+#define   SDR0_PFC1_U0IM_4PINS                 0x00040000      /* UART0 Interface Mode 4 pins */
+#define   SDR0_PFC1_SIS_MASK                   0x00020000    /* SCP or IIC1 Selection */
+#define   SDR0_PFC1_SIS_SCP_SEL                0x00000000      /* SCP Selected */
+#define   SDR0_PFC1_SIS_IIC1_SEL               0x00020000      /* IIC1 Selected */
+#define   SDR0_PFC1_UES_MASK                   0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define   SDR0_PFC1_UES_USB2D_SEL              0x00000000      /* USB2D_RX_Active Selected */
+#define   SDR0_PFC1_UES_EBCHR_SEL              0x00010000      /* EBC_Hold Req Selected */
+#define   SDR0_PFC1_DIS_MASK                   0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define   SDR0_PFC1_DIS_DMAR_SEL               0x00000000      /* DMA_Req(1) Selected */
+#define   SDR0_PFC1_DIS_UICIRQ5_SEL            0x00008000      /* UIC_IRQ(5) Selected */
+#define   SDR0_PFC1_ERE_MASK                   0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define   SDR0_PFC1_ERE_EXTR_SEL               0x00000000      /* EBC Mast.Ext.Req.En. Selected */
+#define   SDR0_PFC1_ERE_GPIO0_27_SEL           0x00004000      /* GPIO0(27) Selected */
+#define   SDR0_PFC1_UPR_MASK                   0x00002000    /* USB2 Device Packet Reject Selection */
+#define   SDR0_PFC1_UPR_DISABLE                0x00000000      /* USB2 Device Packet Reject Disable */
+#define   SDR0_PFC1_UPR_ENABLE                 0x00002000      /* USB2 Device Packet Reject Enable */
+
+#define   SDR0_PFC1_PLB_PME_MASK               0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define   SDR0_PFC1_PLB_PME_PLB3_SEL           0x00000000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_PLB_PME_PLB4_SEL           0x00001000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_GFGGI_MASK                 0x0000000F    /* GPT Frequency Generation Gated In */
+
+/* Ethernet PLL Configuration Register */
+#define SDR0_PFC2                    0x4102
+#define   SDR0_PFC2_TUNE_MASK                  0x01FF8000  /* Loop stability tuning bits */
+#define   SDR0_PFC2_MULTI_MASK                 0x00007C00  /* Frequency multiplication selector */
+#define   SDR0_PFC2_RANGEB_MASK                0x00000380  /* PLLOUTB/C frequency selector */
+#define   SDR0_PFC2_RANGEA_MASK                0x00000071  /* PLLOUTA frequency selector */
+
+#define   SDR0_PFC2_SELECT_MASK                0xE0000000  /* Ethernet Pin select EMAC1 */
+#define   SDR0_PFC2_SELECT_CONFIG_1_1          0x60000000   /* 1xMII   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_1_2          0x00000000   /* 1xMII   using  ZMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_2            0x60000000   /* 1xGMII  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_3            0x80000000   /* 1xTBI   using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_4            0xA0000000   /* 2xRGMII using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_5            0xC0000000   /* 2xRTBI  using RGMII bridge */
+#define   SDR0_PFC2_SELECT_CONFIG_6            0x40000000   /* 2xSMII  using  ZMII bridge */
+
+/* USB2PHY0 Control Register */
+#define SDR0_USB2PHY0CR               0x4103
+#define   SDR0_USB2PHY0CR_UTMICN_MASK          0x00100000 /*  PHY UTMI interface connection */
+#define   SDR0_USB2PHY0CR_UTMICN_DEV           0x00000000  /* Device support */
+#define   SDR0_USB2PHY0CR_UTMICN_HOST          0x00100000  /* Host support */
+
+#define   SDR0_USB2PHY0CR_DWNSTR_MASK          0x00400000 /* Select downstream port mode */
+#define   SDR0_USB2PHY0CR_DWNSTR_DEV           0x00000000  /* Device */
+#define   SDR0_USB2PHY0CR_DWNSTR_HOST          0x00400000  /* Host   */
+
+#define   SDR0_USB2PHY0CR_DVBUS_MASK           0x00800000 /* VBus detect (Device mode only)  */
+#define   SDR0_USB2PHY0CR_DVBUS_PURDIS         0x00000000  /* Pull-up resistance on D+ is disabled */
+#define   SDR0_USB2PHY0CR_DVBUS_PUREN          0x00800000  /* Pull-up resistance on D+ is enabled */
+
+#define   SDR0_USB2PHY0CR_WDINT_MASK           0x01000000 /* PHY UTMI data width and clock select  */
+#define   SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ     0x00000000  /* 8-bit data/60MHz */
+#define   SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ    0x01000000  /* 16-bit data/30MHz */
+
+#define   SDR0_USB2PHY0CR_LOOPEN_MASK          0x02000000 /* Loop back test enable  */
+#define   SDR0_USB2PHY0CR_LOOP_ENABLE          0x00000000  /* Loop back disabled */
+#define   SDR0_USB2PHY0CR_LOOP_DISABLE         0x02000000  /* Loop back enabled (only test purposes) */
+
+#define   SDR0_USB2PHY0CR_XOON_MASK            0x04000000 /* Force XO block on during a suspend  */
+#define   SDR0_USB2PHY0CR_XO_ON                0x00000000  /* PHY XO block is powered-on */
+#define   SDR0_USB2PHY0CR_XO_OFF               0x04000000  /* PHY XO block is powered-off when all ports are suspended */
+
+#define   SDR0_USB2PHY0CR_PWRSAV_MASK          0x08000000 /* Select PHY power-save mode  */
+#define   SDR0_USB2PHY0CR_PWRSAV_OFF           0x00000000  /* Non-power-save mode */
+#define   SDR0_USB2PHY0CR_PWRSAV_ON            0x08000000  /* Power-save mode. Valid only for full-speed operation */
+
+#define   SDR0_USB2PHY0CR_XOREF_MASK           0x10000000 /* Select reference clock source  */
+#define   SDR0_USB2PHY0CR_XOREF_INTERNAL       0x00000000  /* PHY PLL uses chip internal 48M clock as a reference */
+#define   SDR0_USB2PHY0CR_XOREF_XO             0x10000000  /* PHY PLL uses internal XO block output as a reference */
+
+#define   SDR0_USB2PHY0CR_XOCLK_MASK           0x20000000 /* Select clock for XO block  */
+#define   SDR0_USB2PHY0CR_XOCLK_EXTERNAL       0x00000000  /* PHY macro used an external clock */
+#define   SDR0_USB2PHY0CR_XOCLK_CRYSTAL        0x20000000  /* PHY macro uses the clock from a crystal */
+
+#define   SDR0_USB2PHY0CR_CLKSEL_MASK          0xc0000000 /* Select ref clk freq */
+#define   SDR0_USB2PHY0CR_CLKSEL_12MHZ         0x00000000 /* Select ref clk freq = 12 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_48MHZ         0x40000000 /* Select ref clk freq = 48 MHz*/
+#define   SDR0_USB2PHY0CR_CLKSEL_24MHZ         0x80000000 /* Select ref clk freq = 24 MHz*/
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL_MASK   0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH0_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ETH1_CLK_SEL_MASK   0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL_EXT    0x00000000
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00180000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00180000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00100000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
+
+#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
+
 /* CUST0 Customer Configuration Register0 */
 #define SDR0_CUST0                   0x4000
 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
@@ -1007,27 +1243,18 @@
 #define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
 #define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
 
-/* Miscealleneaous Function Reg. */
-#define SDR0_MFR                     0x4300
-#define   SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
-#define   SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
-#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
-#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
-#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
-#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
-#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
-#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
-#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
-#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
-#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
-
-#define   SDR0_MFR_ERRATA3_EN0         0x00800000
-#define   SDR0_MFR_ERRATA3_EN1         0x00400000
-#define   SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
-#define   SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
-#define   SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
-#define   SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
-#define   SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity */
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x380
+#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
 
 #else
 
@@ -1121,7 +1348,7 @@
 #define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
 #define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
 
-#if defined(CONFIG_440SPE)
+#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define UIC2_DCR_BASE 0xe0
 #define uic2sr	(UIC0_DCR_BASE+0x0)   /* UIC2 status-Read Clear		*/
 #define uic2srs	(UIC0_DCR_BASE+0x1)   /* UIC2 status-Read Set */
@@ -1423,6 +1650,46 @@
 #define UIC_EIR6	0x00000004	/* External interrupt 6		    */
 #define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
 #define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_U0        0x80000000  /* UART 0                             */
+#define UIC_U1        0x40000000  /* UART 1                             */
+#define UIC_IIC0      0x20000000  /* IIC                                */
+#define UIC_KRD       0x10000000  /* Kasumi Ready for data              */
+#define UIC_KDA       0x08000000  /* Kasumi Data Available              */
+#define UIC_PCRW      0x04000000  /* PCI command register write         */
+#define UIC_PPM       0x02000000  /* PCI power management               */
+#define UIC_IIC1      0x01000000  /* IIC                                */
+#define UIC_SPI       0x00800000  /* SPI                                */
+#define UIC_EPCISER   0x00400000  /* External PCI SERR                  */
+#define UIC_MTE       0x00200000  /* MAL TXEOB                          */
+#define UIC_MRE       0x00100000  /* MAL RXEOB                          */
+#define UIC_D0        0x00080000  /* DMA channel 0                      */
+#define UIC_D1        0x00040000  /* DMA channel 1                      */
+#define UIC_D2        0x00020000  /* DMA channel 2                      */
+#define UIC_D3        0x00010000  /* DMA channel 3                      */
+#define UIC_UD0       0x00008000  /* UDMA irq 0                         */
+#define UIC_UD1       0x00004000  /* UDMA irq 1                         */
+#define UIC_UD2       0x00002000  /* UDMA irq 2                         */
+#define UIC_UD3       0x00001000  /* UDMA irq 3                         */
+#define UIC_HSB2D     0x00000800  /* USB2.0 Device                      */
+#define UIC_OHCI1     0x00000400  /* USB2.0 Host OHCI irq 1             */
+#define UIC_OHCI2     0x00000200  /* USB2.0 Host OHCI irq 2             */
+#define UIC_EIP94     0x00000100  /* Security EIP94                     */
+#define UIC_ETH0      0x00000080  /* Emac 0                             */
+#define UIC_ETH1      0x00000040  /* Emac 1                             */
+#define UIC_EHCI      0x00000020  /* USB2.0 Host EHCI                   */
+#define UIC_EIR4      0x00000010  /* External interrupt 4               */
+#define UIC_UIC2NC    0x00000008  /* UIC2 non-critical interrupt        */
+#define UIC_UIC2C     0x00000004  /* UIC2 critical interrupt            */
+#define UIC_UIC1NC    0x00000002  /* UIC1 non-critical interrupt        */
+#define UIC_UIC1C     0x00000001  /* UIC1 critical interrupt            */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB	UIC_MTE
+#define UIC_MAL_RXEOB	UIC_MRE
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_U0		0x80000000	/* UART 0			    */
 #define UIC_U1		0x40000000	/* UART 1			    */
@@ -1531,6 +1798,48 @@
 #define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
 #define UIC_ETH1	0x00000002	/* Ethernet 1			    */
 #define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UIC_MS        0x80000000  /* MAL SERR                           */
+#define UIC_MTDE      0x40000000  /* MAL TXDE                           */
+#define UIC_MRDE      0x20000000  /* MAL RXDE                           */
+#define UIC_U2        0x10000000  /* UART 2                             */
+#define UIC_U3        0x08000000  /* UART 3                             */
+#define UIC_EBCO      0x04000000  /* EBCO interrupt status              */
+#define UIC_NDFC      0x02000000  /* NDFC                               */
+#define UIC_KSLE      0x01000000  /* KASUMI slave error                 */
+#define UIC_CT5       0x00800000  /* GPT compare timer 5                */
+#define UIC_CT6       0x00400000  /* GPT compare timer 6                */
+#define UIC_PLB34I0   0x00200000  /* PLB3X4X MIRQ0                      */
+#define UIC_PLB34I1   0x00100000  /* PLB3X4X MIRQ1                      */
+#define UIC_PLB34I2   0x00080000  /* PLB3X4X MIRQ2                      */
+#define UIC_PLB34I3   0x00040000  /* PLB3X4X MIRQ3                      */
+#define UIC_PLB34I4   0x00020000  /* PLB3X4X MIRQ4                      */
+#define UIC_PLB34I5   0x00010000  /* PLB3X4X MIRQ5                      */
+#define UIC_CT0       0x00008000  /* GPT compare timer 0                */
+#define UIC_CT1       0x00004000  /* GPT compare timer 1                */
+#define UIC_EIR7      0x00002000  /* External interrupt 7               */
+#define UIC_EIR8      0x00001000  /* External interrupt 8               */
+#define UIC_EIR9      0x00000800  /* External interrupt 9               */
+#define UIC_CT2       0x00000400  /* GPT compare timer 2                */
+#define UIC_CT3       0x00000200  /* GPT compare timer 3                */
+#define UIC_CT4       0x00000100  /* GPT compare timer 4                */
+#define UIC_SRE       0x00000080  /* Serial ROM error                   */
+#define UIC_GPTDC     0x00000040  /* GPT decrementer pulse              */
+#define UIC_RSVD0     0x00000020  /* Reserved                           */
+#define UIC_EPCIPER   0x00000010  /* External PCI PERR                  */
+#define UIC_EIR0      0x00000008  /* External interrupt 0               */
+#define UIC_EWU0      0x00000004  /* Ethernet 0 wakeup                  */
+#define UIC_EIR1      0x00000002  /* External interrupt 1               */
+#define UIC_EWU1      0x00000001  /* Ethernet 1 wakeup                  */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR	UIC_MS
+#define UIC_MAL_TXDE	UIC_MTDE
+#define UIC_MAL_RXDE	UIC_MRDE
+#define UIC_ENET	UIC_ETH0
+
 #elif !defined(CONFIG_440SPE)
 #define UIC_MS		0x80000000	/* MAL SERR			    */
 #define UIC_MTDE	0x40000000	/* MAL TXDE			    */
@@ -1608,6 +1917,20 @@
 #define UIC_RSVD29	0x00000004	/* Reserved			    */
 #define UIC_RSVD30	0x00000002	/* Reserved			    */
 #define UIC_RSVD31	0x00000001	/* Reserved			    */
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
+
+#define UIC_EIR5    0x80000000  /* External interrupt 5                 */
+#define UIC_EIR6    0x40000000  /* External interrupt 6                 */
+#define UIC_OPB     0x20000000  /* OPB to PLB bridge interrupt stat     */
+#define UIC_EIR2    0x10000000  /* External interrupt 2                 */
+#define UIC_EIR3    0x08000000  /* External interrupt 3                 */
+#define UIC_DDR2    0x04000000  /* DDR2 sdram                           */
+#define UIC_MCTX0   0x02000000  /* MAl intp coalescence TX0             */
+#define UIC_MCTX1   0x01000000  /* MAl intp coalescence TX1             */
+#define UIC_MCTR0   0x00800000  /* MAl intp coalescence TR0             */
+#define UIC_MCTR1   0x00400000  /* MAl intp coalescence TR1             */
+
 #endif	/* CONFIG_440GX */
 
 /*---------------------------------------------------------------------------+
@@ -1623,6 +1946,17 @@
 
 #define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
 						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+#define UICB0_UIC1CI	0x00000000	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x00000000	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x00000000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x00000000	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL		(UICB0_UIC1CI | UICB0_UIC1NCI | \
+						 UICB0_UIC1CI | UICB0_UIC2NCI)
+
 #endif /* CONFIG_440GX */
 /*---------------------------------------------------------------------------+
 |  Universal interrupt controller interrupts
@@ -2262,7 +2596,8 @@
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
 #define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
 #define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
@@ -2390,11 +2725,81 @@
 #define SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
 #define SDR0_MFR_ERRATA3_EN0         0x00800000
 #define SDR0_MFR_ERRATA3_EN1         0x00400000
+#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
 #define SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
 #define SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
 #define SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
 #define SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
 #define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
+#endif
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_PFC1_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n)		((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC2_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<29)
+#define SDR0_PFC2_EPS_DECODE(n)		((((unsigned long)(n))>>29)&0x07)
+#endif
+
+#define SDR0_MFR_ECS_MASK		0x10000000
+#define SDR0_MFR_ECS_INTERNAL		0x10000000
+
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define SDR0_SRST0        0x200
+#define SDR0_SRST0_BGO          0x80000000 /* PLB to OPB bridge */
+#define SDR0_SRST0_PLB4         0x40000000 /* PLB4 arbiter */
+#define SDR0_SRST0_EBC          0x20000000 /* External bus controller */
+#define SDR0_SRST0_OPB          0x10000000 /* OPB arbiter */
+#define SDR0_SRST0_UART0        0x08000000 /* Universal asynchronous receiver/transmitter 0 */
+#define SDR0_SRST0_UART1        0x04000000 /* Universal asynchronous receiver/transmitter 1 */
+#define SDR0_SRST0_IIC0         0x02000000 /* Inter integrated circuit 0 */
+#define SDR0_SRST0_USB2H        0x01000000 /* USB2.0 Host */
+#define SDR0_SRST0_GPIO         0x00800000 /* General purpose I/O */
+#define SDR0_SRST0_GPT          0x00400000 /* General purpose timer */
+#define SDR0_SRST0_DMC          0x00200000 /* DDR SDRAM memory controller */
+#define SDR0_SRST0_PCI          0x00100000 /* PCI */
+#define SDR0_SRST0_EMAC0        0x00080000 /* Ethernet media access controller 0 */
+#define SDR0_SRST0_EMAC1        0x00040000 /* Ethernet media access controller 1 */
+#define SDR0_SRST0_CPM0         0x00020000 /* Clock and power management */
+#define SDR0_SRST0_ZMII         0x00010000 /* ZMII bridge */
+#define SDR0_SRST0_UIC0         0x00008000 /* Universal interrupt controller 0 */
+#define SDR0_SRST0_UIC1         0x00004000 /* Universal interrupt controller 1 */
+#define SDR0_SRST0_IIC1         0x00002000 /* Inter integrated circuit 1 */
+#define SDR0_SRST0_SCP          0x00001000 /* Serial communications port */
+#define SDR0_SRST0_BGI          0x00000800 /* OPB to PLB bridge */
+#define SDR0_SRST0_DMA          0x00000400 /* Direct memory access controller */
+#define SDR0_SRST0_DMAC         0x00000200 /* DMA channel */
+#define SDR0_SRST0_MAL          0x00000100 /* Media access layer */
+#define SDR0_SRST0_USB2D        0x00000080 /* USB2.0 device */
+#define SDR0_SRST0_GPTR         0x00000040 /* General purpose timer */
+#define SDR0_SRST0_P4P3         0x00000010 /* PLB4 to PLB3 bridge */
+#define SDR0_SRST0_P3P4         0x00000008 /* PLB3 to PLB4 bridge */
+#define SDR0_SRST0_PLB3         0x00000004 /* PLB3 arbiter */
+#define SDR0_SRST0_UART2        0x00000002 /* Universal asynchronous receiver/transmitter 2 */
+#define SDR0_SRST0_UART3        0x00000001 /* Universal asynchronous receiver/transmitter 3 */
+
+#define SDR0_SRST1        0x201
+#define SDR0_SRST1_NDFC         0x80000000 /* Nand flash controller */
+#define SDR0_SRST1_OPBA1        0x40000000 /* OPB Arbiter attached to PLB4 */
+#define SDR0_SRST1_P4OPB0       0x20000000 /* PLB4 to OPB Bridge0 */
+#define SDR0_SRST1_PLB42OPB0    SDR0_SRST1_P4OPB0
+#define SDR0_SRST1_DMA4         0x10000000 /* DMA to PLB4 */
+#define SDR0_SRST1_DMA4CH       0x08000000 /* DMA Channel to PLB4 */
+#define SDR0_SRST1_OPBA2        0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
+#define SDR0_SRST1_OPB2PLB40    0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_PLB42OPB1    0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
+#define SDR0_SRST1_CPM1         0x00800000 /* Clock and Power management 1 */
+#define SDR0_SRST1_UIC2         0x00400000 /* Universal Interrupt Controller 2 */
+#define SDR0_SRST1_CRYP0        0x00200000 /* Security Engine */
+#define SDR0_SRST1_USB20PHY     0x00100000 /* USB 2.0 Phy */
+#define SDR0_SRST1_USB2HUTMI    0x00080000 /* USB 2.0 Host UTMI Interface */
+#define SDR0_SRST1_USB2HPHY     0x00040000 /* USB 2.0 Host Phy Interface */
+#define SDR0_SRST1_SRAM0        0x00020000 /* Internal SRAM Controller */
+#define SDR0_SRST1_RGMII0       0x00010000 /* RGMII Bridge */
+#define SDR0_SRST1_ETHPLL       0x00008000 /* Ethernet PLL */
+#define SDR0_SRST1_FPU          0x00004000 /* Floating Point Unit */
+#define SDR0_SRST1_KASU0        0x00002000 /* Kasumi Engine */
+
+#else
 
 #define SDR0_SRST_BGO			0x80000000
 #define SDR0_SRST_PLB			0x40000000
@@ -2427,10 +2832,15 @@
 #define SDR0_SRST_EMAC3			0x00000008
 #define SDR0_SRST_RGMII			0x00000001
 
+#endif
+
 /*-----------------------------------------------------------------------------+
 |  Clocking
 +-----------------------------------------------------------------------------*/
-#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
+#if !defined (CONFIG_440GX) && \
+    !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
+    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
+    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 #define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
 #define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
 #define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
@@ -2498,6 +2908,120 @@
 #define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
 #endif /* CONFIG_440GX */
 
+#if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
+/*--------------------------------------*/
+#define CPR0_PLLC                   0x40
+#define   CPR0_PLLC_RST_MASK           0x80000000
+#define   CPR0_PLLC_RST_PLLLOCKED      0x00000000
+#define   CPR0_PLLC_RST_PLLRESET       0x80000000
+#define   CPR0_PLLC_ENG_MASK           0x40000000
+#define   CPR0_PLLC_ENG_DISABLE        0x00000000
+#define   CPR0_PLLC_ENG_ENABLE         0x40000000
+#define   CPR0_PLLC_ENG_ENCODE(n)      ((((unsigned long)(n))&0x01)<<30)
+#define   CPR0_PLLC_ENG_DECODE(n)      ((((unsigned long)(n))>>30)&0x01)
+#define   CPR0_PLLC_SRC_MASK           0x20000000
+#define   CPR0_PLLC_SRC_PLLOUTA        0x00000000
+#define   CPR0_PLLC_SRC_PLLOUTB        0x20000000
+#define   CPR0_PLLC_SRC_ENCODE(n)      ((((unsigned long)(n))&0x01)<<29)
+#define   CPR0_PLLC_SRC_DECODE(n)      ((((unsigned long)(n))>>29)&0x01)
+#define   CPR0_PLLC_SEL_MASK           0x07000000
+#define   CPR0_PLLC_SEL_PLL            0x00000000
+#define   CPR0_PLLC_SEL_CPU            0x01000000
+#define   CPR0_PLLC_SEL_PER            0x05000000
+#define   CPR0_PLLC_SEL_ENCODE(n)      ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PLLC_SEL_DECODE(n)      ((((unsigned long)(n))>>24)&0x07)
+#define   CPR0_PLLC_TUNE_MASK          0x000003FF
+#define   CPR0_PLLC_TUNE_ENCODE(n)     ((((unsigned long)(n))&0x3FF)<<0)
+#define   CPR0_PLLC_TUNE_DECODE(n)     ((((unsigned long)(n))>>0)&0x3FF)
+/*--------------------------------------*/
+#define CPR0_PLLD                   0x60
+#define   CPR0_PLLD_FBDV_MASK          0x1F000000
+#define   CPR0_PLLD_FBDV_ENCODE(n)     ((((unsigned long)(n))&0x1F)<<24)
+#define   CPR0_PLLD_FBDV_DECODE(n)     ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
+#define   CPR0_PLLD_FWDVA_MASK         0x000F0000
+#define   CPR0_PLLD_FWDVA_ENCODE(n)    ((((unsigned long)(n))&0x0F)<<16)
+#define   CPR0_PLLD_FWDVA_DECODE(n)    ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
+#define   CPR0_PLLD_FWDVB_MASK         0x00000700
+#define   CPR0_PLLD_FWDVB_ENCODE(n)    ((((unsigned long)(n))&0x07)<<8)
+#define   CPR0_PLLD_FWDVB_DECODE(n)    ((((((unsigned long)(n))>>8)-1)&0x07)+1)
+#define   CPR0_PLLD_LFBDV_MASK         0x0000003F
+#define   CPR0_PLLD_LFBDV_ENCODE(n)    ((((unsigned long)(n))&0x3F)<<0)
+#define   CPR0_PLLD_LFBDV_DECODE(n)    ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMAD                 0x80
+#define   CPR0_PRIMAD_PRADV0_MASK      0x07000000
+#define   CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_PRIMBD                 0xA0
+#define   CPR0_PRIMBD_PRBDV0_MASK      0x07000000
+#define   CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#if 0
+#define CPR0_CPM0_ER                0xB0    /* CPM Enable Register */
+#define CPR0_CPM0_FR                0xB1    /* CPM Force Register */
+#define CPR0_CPM0_SR                0xB2    /* CPM Status Register */
+#define CPR0_CPM0_IIC0               0x80000000    /* Inter-Intergrated Circuit0 */
+#define CPR0_CPM0_IIC1               0x40000000    /* Inter-Intergrated Circuit1 */
+#define CPR0_CPM0_PCI                0x20000000    /* Peripheral Component Interconnect */
+#define CPR0_CPM0_USB1H              0x08000000    /* USB1.1 Host */
+#define CPR0_CPM0_FPU                0x04000000    /* PPC440 FPU */
+#define CPR0_CPM0_CPU                0x02000000    /* PPC440x5 Processor Core */
+#define CPR0_CPM0_DMA                0x01000000    /* Direct Memory Access Controller */
+#define CPR0_CPM0_BGO                0x00800000    /* PLB to OPB Bridge */
+#define CPR0_CPM0_BGI                0x00400000    /* OPB to PLB Bridge */
+#define CPR0_CPM0_EBC                0x00200000    /* External Bus Controller */
+#define CPR0_CPM0_NDFC               0x00100000    /* Nand Flash Controller */
+#define CPR0_CPM0_MADMAL             0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_DMC                0x00080000    /* DDR SDRAM Controller or MADMAL ??? */
+#define CPR0_CPM0_PLB4               0x00040000    /* PLB4 Arbiter */
+#define CPR0_CPM0_PLB4x3x            0x00020000    /* PLB4 to PLB3 */
+#define CPR0_CPM0_PLB3x4x            0x00010000    /* PLB3 to PLB4 */
+#define CPR0_CPM0_PLB3               0x00008000    /* PLB3 Arbiter */
+#define CPR0_CPM0_PPM                0x00002000    /* PLB Performance Monitor */
+#define CPR0_CPM0_UIC1               0x00001000    /* Universal Interrupt Controller 1 */
+#define CPR0_CPM0_GPIO               0x00000800    /* General Purpose IO */
+#define CPR0_CPM0_GPT                0x00000400    /* General Purpose Timer */
+#define CPR0_CPM0_UART0              0x00000200    /* Universal Asynchronous Rcver/Xmitter 0 */
+#define CPR0_CPM0_UART1              0x00000100    /* Universal Asynchronous Rcver/Xmitter 1 */
+#define CPR0_CPM0_UIC0               0x00000080    /* Universal Interrupt Controller 0 */
+#define CPR0_CPM0_TMRCLK             0x00000040    /* CPU Timer */
+#define CPR0_CPM0_EMC0               0x00000020    /* Ethernet 0 */
+#define CPR0_CPM0_EMC1               0x00000010    /* Ethernet 1 */
+#define CPR0_CPM0_UART2              0x00000008    /* Universal Asynchronous Rcver/Xmitter 2 */
+#define CPR0_CPM0_UART3              0x00000004    /* Universal Asynchronous Rcver/Xmitter 3 */
+#define CPR0_CPM0_USB2D              0x00000002    /* USB2.0 Device */
+#define CPR0_CPM0_USB2H              0x00000001    /* USB2.0 Host */
+#endif
+/*--------------------------------------*/
+#define CPR0_OPBD                   0xC0
+#define   CPR0_OPBD_OPBDV0_MASK        0x03000000
+#define   CPR0_OPBD_OPBDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_OPBD_OPBDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_PERD                   0xE0
+#define   CPR0_PERD_PERDV0_MASK        0x07000000
+#define   CPR0_PERD_PERDV0_ENCODE(n)   ((((unsigned long)(n))&0x07)<<24)
+#define   CPR0_PERD_PERDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x07)+1)
+/*--------------------------------------*/
+#define CPR0_MALD                  0x100
+#define   CPR0_MALD_MALDV0_MASK        0x03000000
+#define   CPR0_MALD_MALDV0_ENCODE(n)   ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_MALD_MALDV0_DECODE(n)   ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_SPCID                 0x120
+#define   CPR0_SPCID_SPCIDV0_MASK      0x03000000
+#define   CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
+#define   CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
+/*--------------------------------------*/
+#define CPR0_ICFG                  0x140
+#define   CPR0_ICFG_RLI_MASK           0x80000000
+#define   CPR0_ICFG_RLI_RESETCPR       0x00000000
+#define   CPR0_ICFG_RLI_PRESERVECPR    0x80000000
+#define   CPR0_ICFG_ICS_MASK           0x00000007
+#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
+
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
@@ -2539,7 +3063,8 @@
 #define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
 #define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* PCI Local Configuration Registers
    --------------------------------- */
@@ -2625,6 +3150,33 @@
 
 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+
+/* USB2.0 Device */
+#define USB2D0_BASE         CFG_USB2D0_BASE
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000)
+
+#define USB2D0_INTRIN       (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
+#define USB2D0_POWER        (USB2D0_BASE + 0x00000000) /* Power management register */
+#define USB2D0_FADDR        (USB2D0_BASE + 0x00000000) /* Function address register */
+#define USB2D0_INTRINE      (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
+#define USB2D0_INTROUT      (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
+#define USB2D0_INTRUSBE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
+#define USB2D0_INTRUSB      (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
+#define USB2D0_INTROUTE     (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
+#define USB2D0_TSTMODE      (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
+#define USB2D0_INDEX        (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
+#define USB2D0_FRAME        (USB2D0_BASE + 0x00000000) /* Frame number */
+#define USB2D0_INCSR0       (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
+#define USB2D0_INCSR        (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_INMAXP       (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCSR       (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTMAXP      (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
+#define USB2D0_OUTCOUNT0    (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
+#define USB2D0_OUTCOUNT     (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
+#endif
+
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
@@ -2640,7 +3192,8 @@
 #define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
 #define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index ec2e3629bb8..43c5ca451e0 100644
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -145,12 +145,14 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_STACR_OC_MASK	(0x00000000)
 #endif
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_PFC1_EM_1000	(0x00200000)
 #endif
 
 /*ZMII Bridge Register addresses */
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
 #else
 #define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
@@ -163,6 +165,7 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_MDI0			0x80000000
 
 /* ZMII FER Register Bit Definitions */
+#define ZMII_FER_DIS		(0x0)
 #define ZMII_FER_MDI		(0x8)
 #define ZMII_FER_SMII		(0x4)
 #define ZMII_FER_RMII		(0x2)
@@ -197,7 +200,11 @@ typedef struct emac_4xx_hw_st {
 #define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
 
 /* RGMII Register Addresses */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x1000)
+#else
 #define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#endif
 #define RGMII_FER		(RGMII_BASE + 0x00)
 #define RGMII_SSR		(RGMII_BASE + 0x04)
 
@@ -216,7 +223,11 @@ typedef struct emac_4xx_hw_st {
 #define RGMII_SSR_SP_100MBPS	(0x02)
 #define RGMII_SSR_SP_1000MBPS	(0x04)
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define RGMII_SSR_V(__x)	((__x) * 8)
+#else
 #define RGMII_SSR_V(__x)	((__x -2) * 8)
+#endif
 
 
 /*---------------------------------------------------------------------------+
@@ -286,7 +297,8 @@ typedef struct emac_4xx_hw_st {
 
 /* Ethernet MAC Regsiter Addresses */
 #if defined(CONFIG_440)
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
 #else
 #define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
@@ -332,7 +344,9 @@ typedef struct emac_4xx_hw_st {
 #define EMAC_M0_WKE			    (0x04000000)
 
 /* on 440GX EMAC_MR1 has a different layout! */
-#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#if defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 /* MODE Reg 1 */
 #define EMAC_M1_FDE		(0x80000000)
 #define EMAC_M1_ILE		(0x40000000)
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 72d690ef0f8..3e47e82abad 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -312,7 +312,7 @@ label:                                                  \
 	lwz     r3,GOT(transfer_to_handler);            \
 	mtlr    r3;                                     \
 	addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-	li      r20,MSR_KERNEL;                         \
+	li      r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
 	rlwimi  r20,r23,0,25,25;                        \
 	blrl    ;                                       \
 .L_ ## label :                                          \
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index db80f775603..cf0e3fdf4b6 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -763,6 +763,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	spi_init_r ();
 #endif
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	WATCHDOG_RESET ();
+	puts ("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate ();
 
@@ -959,12 +965,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	doc_init ();
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-	WATCHDOG_RESET ();
-	puts ("NAND:  ");
-	nand_init();		/* go init the NAND */
-#endif
-
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 #if defined(CONFIG_NET_MULTI)
 	WATCHDOG_RESET ();
diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile
new file mode 100644
index 00000000000..6c07e3dd8df
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/Makefile
@@ -0,0 +1,83 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+include board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o init.o resetvec.o
+COBJS	= nand_boot.o ndfc.o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+ALL	= u-boot-spl u-boot-spl.bin u-boot-spl-4k.bin
+
+all:	$(obj).depend $(ALL)
+
+u-boot-spl-4k.bin: u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+u-boot-spl.bin:	u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+u-boot-spl:	$(OBJS)
+	$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
+		-Map u-boot-spl.map -o u-boot-spl
+
+# create symbolic links for common files
+
+# from cpu directory
+ndfc.c:
+	@rm -f ndfc.c
+	ln -s ../cpu/ppc4xx/ndfc.c ndfc.c
+
+resetvec.S:
+	@rm -f resetvec.S
+	ln -s ../cpu/ppc4xx/resetvec.S resetvec.S
+
+start.S:
+	@rm -f start.S
+	ln -s ../cpu/ppc4xx/start.S start.S
+
+# from board directory
+init.S:
+	@rm -f init.S
+	ln -s ../board/amcc/sequoia/init.S init.S
+
+sdram.c:
+	@rm -f sdram.c
+	ln -s ../board/amcc/sequoia/sdram.c sdram.c
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/amcc/sequoia/config.mk b/nand_spl/board/amcc/sequoia/config.mk
new file mode 100644
index 00000000000..a29ba5fd0dc
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/config.mk
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+#
+# TEXT_BASE for SPL:
+#
+# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
+# in the last 4kBytes of memory space in cache.
+# We will copy this SPL into internal SRAM in start.S. So we set
+# TEXT_BASE to starting address in internal SRAM here.
+#
+TEXT_BASE = 0xE0013000
+
+# PAD_TO used to generate a 16kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x4000
+PAD_TO	= 0xE0017000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds
new file mode 100644
index 00000000000..156368911a2
--- /dev/null
+++ b/nand_spl/board/amcc/sequoia/u-boot.lds
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc:common)
+SECTIONS
+{
+  .resetvec 0xE0013FFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .text      :
+  {
+    start.o	(.text)
+    init.o	(.text)
+    nand_boot.o	(.text)
+    sdram.o	(.text)
+    ndfc.o	(.text)
+
+    *(.text)
+    *(.fixup)
+  }
+  _etext = .;
+
+  .data    :
+  {
+    *(.rodata*)
+    *(.data*)
+    *(.sdata*)
+    __got2_start = .;
+    *(.got2)
+    __got2_end = .;
+  }
+
+  _edata  =  .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss)
+   *(.bss)
+  }
+
+  _end = . ;
+}
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
new file mode 100644
index 00000000000..6e3af13939f
--- /dev/null
+++ b/nand_spl/nand_boot.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+
+#define CFG_NAND_READ_DELAY \
+	{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
+
+extern void board_nand_init(struct nand_chip *nand);
+extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd);
+extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte);
+extern u_char ndfc_read_byte(struct mtd_info *mtdinfo);
+extern int ndfc_dev_ready(struct mtd_info *mtdinfo);
+extern int jump_to_ram(ulong delta);
+extern int jump_to_uboot(ulong addr);
+
+static int nand_is_bad_block(struct mtd_info *mtd, int block)
+{
+        struct nand_chip *this = mtd->priv;
+	int page_addr = block * CFG_NAND_PAGE_COUNT;
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, NAND_CMD_READOOB);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS);			/* A[7:0] */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[16:9] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+	/* One more address cycle for devices > 32MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:25] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/*
+	 * Read on byte
+	 */
+	if (this->read_byte(mtd) != 0xff)
+		return 1;
+
+	return 0;
+}
+
+static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
+{
+        struct nand_chip *this = mtd->priv;
+	int page_addr = page + block * CFG_NAND_PAGE_COUNT;
+	int i;
+
+	/* Begin command latch cycle */
+	this->hwcontrol(mtd, NAND_CTL_SETCLE);
+	this->write_byte(mtd, NAND_CMD_READ0);
+	/* Set ALE and clear CLE to start address cycle */
+	this->hwcontrol(mtd, NAND_CTL_CLRCLE);
+	this->hwcontrol(mtd, NAND_CTL_SETALE);
+	/* Column address */
+	this->write_byte(mtd, 0);					/* A[7:0] */
+	this->write_byte(mtd, (uchar)(page_addr & 0xff));		/* A[16:9] */
+	this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff));	/* A[24:17] */
+#ifdef CFG_NAND_4_ADDR_CYCLE
+	/* One more address cycle for devices > 32MiB */
+	this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f));	/* A[xx:25] */
+#endif
+	/* Latch in address */
+	this->hwcontrol(mtd, NAND_CTL_CLRALE);
+
+	/*
+	 * Wait a while for the data to be ready
+	 */
+	if (this->dev_ready)
+		this->dev_ready(mtd);
+	else
+		CFG_NAND_READ_DELAY;
+
+	/*
+	 * Read page into buffer
+	 */
+	for (i=0; i<CFG_NAND_PAGE_SIZE; i++)
+		*dst++ = this->read_byte(mtd);
+
+	return 0;
+}
+
+static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
+{
+	int block;
+	int blockcopy_count;
+	int page;
+
+	/*
+	 * offs has to be aligned to a block address!
+	 */
+	block = offs / CFG_NAND_BLOCK_SIZE;
+	blockcopy_count = 0;
+
+	while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
+		if (!nand_is_bad_block(mtd, block)) {
+			/*
+			 * Skip bad blocks
+			 */
+			for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
+				nand_read_page(mtd, block, page, dst);
+				dst += CFG_NAND_PAGE_SIZE;
+			}
+
+			blockcopy_count++;
+		}
+
+		block++;
+	}
+
+	return 0;
+}
+
+void nand_boot(void)
+{
+	ulong mem_size;
+	struct nand_chip nand_chip;
+	nand_info_t nand_info;
+	int ret;
+	void (*uboot)(void);
+
+	/*
+	 * Init sdram, so we have access to memory
+	 */
+	mem_size = initdram(0);
+
+	/*
+	 * Init board specific nand support
+	 */
+	nand_info.priv = &nand_chip;
+	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CFG_NAND_BASE;
+	nand_chip.dev_ready = NULL;	/* preset to NULL */
+	board_nand_init(&nand_chip);
+
+	/*
+	 * Load U-Boot image from NAND into RAM
+	 */
+	ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS,
+			CFG_NAND_U_BOOT_SIZE,
+			(uchar *)CFG_NAND_U_BOOT_DST);
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void (*)(void))CFG_NAND_U_BOOT_START;
+	(*uboot)();
+}