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authorMarcel Ziswiler <marcel.ziswiler@toradex.com>2015-04-28 02:05:32 +0200
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2017-01-11 21:27:14 +0100
commit89a14c2f11e3f3eb4fcc028c6864ed5fa8bae74b (patch)
tree915b5969a1f8b19392a1192564c7c88b66d203ef
parent59b9b3dfb10d917a60844b127557bb6499fb5249 (diff)
tegra: nand: 16-bit bch ecc integration
Integrate 16-bit BCH ECC handling required e.g. for the latest NAND parts assembled on Colibri T20. (cherry picked from commit dcca76ea36fc778fa750473aee09fa0297dc5e2b)
-rw-r--r--drivers/mtd/nand/tegra_nand.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 5c9b485b082..e6dbdbbf2c1 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -539,18 +539,14 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
chip->ecc.layout->oobavail + TAG_ECC_BYTES);
tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
reg_val |= (CFG_SKIP_SPARE_SEL_4
- | CFG_SKIP_SPARE_ENABLE
- | CFG_HW_ECC_CORRECTION_ENABLE
- | CFG_ECC_EN_TAG_DISABLE
- | CFG_HW_ECC_SEL_RS
- | CFG_HW_ECC_ENABLE
- | CFG_TVAL4
- | (tag_size - 1));
+ | CFG_SKIP_SPARE_ENABLE);
if (!is_writing)
tag_size += SKIPPED_SPARE_BYTES;
bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
bbflags);
+ writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
+ writel(BCH_CONFIG_BCH_TVAL16 | BCH_CONFIG_BCH_ECC_ENABLE, &info->reg->bch_config);
} else {
tag_size = mtd->oobsize;
reg_val |= (CFG_SKIP_SPARE_DISABLE
@@ -560,10 +556,10 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
| (tag_size - 1));
bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
tag_size, bbflags);
+ writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
+ writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
}
writel(reg_val, &info->reg->config);
- writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
- writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
writel(tag_size - 1, &info->reg->dma_cfg_b);
nand_clear_interrupt_status(info->reg);
@@ -572,7 +568,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
| CMD_SEC_CMD
| (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
| CMD_A_VALID
- | CMD_B_VALID
+ | (with_ecc ? 0 : CMD_B_VALID)
| (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
| CMD_CE0;
if (!is_writing)
@@ -585,7 +581,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
reg_val = DMA_MST_CTRL_GO_ENABLE
| DMA_MST_CTRL_BURST_8WORDS
| DMA_MST_CTRL_EN_A_ENABLE
- | DMA_MST_CTRL_EN_B_ENABLE;
+ | (with_ecc ? 0 : DMA_MST_CTRL_EN_B_ENABLE);
if (!is_writing)
reg_val |= DMA_MST_CTRL_DIR_READ;