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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-08-08 08:11:43 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2017-08-31 19:57:26 -0700 |
| commit | 2c81b821cd50d27afca22b07d5f4f04212703649 (patch) | |
| tree | 31561c0465d1a7e00e874ec639638c0e6bc25a9f | |
| parent | 60b8a4fb2e3a5ccb1d610e1c7bed6da8e08ebba3 (diff) | |
apalis_t30: describe pcie ports
Add some more comments describing the various PCIe ports available.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm/dts/tegra30-apalis.dts | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra30-apalis.dts b/arch/arm/dts/tegra30-apalis.dts index 5b02b260384..11e6026bcd1 100644 --- a/arch/arm/dts/tegra30-apalis.dts +++ b/arch/arm/dts/tegra30-apalis.dts @@ -43,16 +43,19 @@ vddio-pex-ctl-supply = <&sys_3v3_reg>; hvdd-pex-supply = <&sys_3v3_reg>; + /* Apalis Type Specific 4 Lane PCIe */ pci@1,0 { /* TS_DIFF1/2/3/4 left disabled */ nvidia,num-lanes = <4>; }; + /* Apalis PCIe */ pci@2,0 { /* PCIE1_RX/TX left disabled */ nvidia,num-lanes = <1>; }; + /* I210 Gigabit Ethernet Controller (On-module) */ pci@3,0 { status = "okay"; nvidia,num-lanes = <1>; |