diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2006-05-30 08:51:19 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@jdl.com> | 2006-05-30 08:51:19 -0500 |
| commit | 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a (patch) | |
| tree | 4a6f5d50de773597cfd7865783c91ce42adc8f0c | |
| parent | d11fec5015334deb2010e36ce00bb118cc5429a5 (diff) | |
Fix two SDRAM setup bugs.
Fix ECC setup bug.
Enable 1T/2T based on number of DIMMs present.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| -rw-r--r-- | cpu/mpc86xx/spd_sdram.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 130c8fc3961..f30bbbd7e2b 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num) * If the user wanted ECC (enabled via sdram_cfg[2]) */ if (config == 0x02) { + ddr->err_disable = 0x00000000; + asm("sync;isync;"); + ddr->err_sbe = 0x00ff0000; + ddr->err_int_en = 0x0000000d; sdram_cfg_1 |= 0x20000000; /* ECC_EN */ } #endif /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. + * Set 1T or 2T timing based on 1 or 2 modules */ { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) + if (!(no_dimm1 || no_dimm2)) { /* + * 2T timing,because both DIMMS are present. * Enable 2T timing by setting sdram_cfg[16]. */ sdram_cfg_1 |= 0x8000; /* 2T_EN */ -#endif } } |