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authorWolfgang Denk <wd@denx.de>2012-07-12 08:17:29 +0200
committerWolfgang Denk <wd@denx.de>2012-07-12 08:17:29 +0200
commit0b15d51ed07db4c318d9c6b02b394ba5a3bc4296 (patch)
tree1a944f7da01e951b473959b6995c1aedce92260b
parenta0bc44e68ef696ba48731aadf433f80315bdafa7 (diff)
parent175a7d2778ad26a244f5c846a6385413c87d95a7 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-i2c
* 'master' of git://git.denx.de/u-boot-i2c: mx28evk: Add I2C support mxs-i2c: Fix internal address byte order mxc_i2c: remove setting speed at each start mx6qsabrelite: add i2c support mxc_i2c: specify i2c base address in config file Signed-off-by: Wolfgang Denk <wd@denx.de>
-rw-r--r--arch/arm/include/asm/arch-mx31/imx-regs.h7
-rw-r--r--arch/arm/include/asm/arch-mx35/imx-regs.h2
-rw-r--r--board/freescale/mx28evk/iomux.c3
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c11
-rw-r--r--drivers/i2c/mxc_i2c.c31
-rw-r--r--drivers/i2c/mxs_i2c.c2
-rw-r--r--include/configs/flea3.h2
-rw-r--r--include/configs/imx31_phycore.h3
-rw-r--r--include/configs/mx28evk.h8
-rw-r--r--include/configs/mx35pdk.h2
-rw-r--r--include/configs/mx53ard.h2
-rw-r--r--include/configs/mx53evk.h2
-rw-r--r--include/configs/mx53loco.h2
-rw-r--r--include/configs/mx53smd.h2
-rw-r--r--include/configs/mx6qsabrelite.h8
15 files changed, 51 insertions, 36 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6454acbd42..7ddbbd627c 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -606,6 +606,13 @@ struct esdc_regs {
#define UART4_BASE 0x43FB0000
#define UART5_BASE 0x43FB4000
+#define I2C1_BASE_ADDR 0x43f80000
+#define I2C1_CLK_OFFSET 26
+#define I2C2_BASE_ADDR 0x43F98000
+#define I2C2_CLK_OFFSET 28
+#define I2C3_BASE_ADDR 0x43f84000
+#define I2C3_CLK_OFFSET 30
+
#define ESDCTL_SDE (1 << 31)
#define ESDCTL_CMD_RW (0 << 28)
#define ESDCTL_CMD_PRECHARGE (1 << 28)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index e570ad1e36..314600621c 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -39,7 +39,7 @@
#define MAX_BASE_ADDR 0x43F04000
#define EVTMON_BASE_ADDR 0x43F08000
#define CLKCTL_BASE_ADDR 0x43F0C000
-#define I2C_BASE_ADDR 0x43F80000
+#define I2C1_BASE_ADDR 0x43F80000
#define I2C3_BASE_ADDR 0x43F84000
#define ATA_BASE_ADDR 0x43F8C000
#define UART1_BASE 0x43F90000
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 00cc0cc2fa..40d8cf6097 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -159,6 +159,9 @@ const iomux_cfg_t iomux_setup[] = {
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
};
#define HW_DRAM_CTL29 (0x74 >> 2)
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 29cbfed120..0eae96d3a3 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -55,6 +55,11 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -72,6 +77,11 @@ iomux_v3_cfg_t uart2_pads[] = {
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+iomux_v3_cfg_t i2c3_pads[] = {
+ MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+};
+
iomux_v3_cfg_t usdhc3_pads[] = {
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -336,6 +346,7 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
#ifdef CONFIG_CMD_SATA
setup_sata();
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c88ac7cf98..fc68062b11 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -59,27 +59,10 @@ struct mxc_i2c_regs {
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE 0x43f80000
-#define I2C_CLK_OFFSET 26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE 0x43f98000
-#define I2C_CLK_OFFSET 28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE 0x43f84000
-#define I2C_CLK_OFFSET 30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE CONFIG_SYS_I2C_BASE
#else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
#define I2C_MAX_TIMEOUT 10000
@@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
(struct clock_control_regs *)CCM_BASE;
/* start the required I2C clock */
- writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+ writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
&sc_regs->cgr0);
#endif
@@ -248,12 +231,6 @@ int i2c_imx_start(void)
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
int result;
- int speed = i2c_get_bus_speed();
- u8 clk_idx = i2c_imx_get_clk(speed);
- u8 idx = i2c_clk_div[clk_idx][1];
-
- /* Store divider value */
- writeb(idx, &i2c_regs->ifdr);
/* Enable I2C controller */
writeb(0, &i2c_regs->i2sr);
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index c8fea32355..48aaaa6268 100644
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
@@ -97,7 +97,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen,
for (i = 0; i < alen; i++) {
data >>= 8;
- data |= ((char *)&addr)[i] << 24;
+ data |= ((char *)&addr)[alen - i - 1] << 24;
if ((i & 3) == 2)
writel(data, &i2c_regs->hw_i2c_data);
}
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 6c5fcac6c1..e8e3c6a03d 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -66,7 +66,7 @@
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index acbd6701c7..a412cf61ee 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -54,7 +54,8 @@
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_UART
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 8f60496d35..54d21e687a 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -68,6 +68,7 @@
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_I2C
/*
* Memory configurations
@@ -188,6 +189,13 @@
#define CONFIG_USB_STORAGE
#endif
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
/*
* SPI
*/
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index ebbd371165..f930ed0a67 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -57,7 +57,7 @@
*/
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index ffc799cd7f..0a928afc82 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -50,7 +50,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 8f2c03f1a0..67def93f63 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -53,7 +53,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2 1
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Configs */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index e71148dee6..61ecd02e4c 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -89,7 +89,7 @@
/* I2C Configs */
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* PMIC Controller */
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 1df20faf6b..760014fce5 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -50,7 +50,7 @@
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index fd25fafeab..fbd10d670f 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -58,6 +58,14 @@
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC